Addressable shadow port and protocol for serial bus networks

Claim 1

Circuitry for providing an improved method of operating a serial test bus in a system environment, comprising: a system backplane having a serial test bus and slots for one or more boards; a plurality of boards installed in said system backplane, each one of said boards having a local serial test bus coupled to a plurality of integrated circuits, and each one of said boards having an addressable shadow port coupled to said local serial test bus and to said system backplane serial test bus, and each one of said addressable shadow ports on said boards being assigned a unique address on said system backplane; and a serial bus master coupled to said system backplane serial test bus, operable to communicate with a selected one of said plurality of boards by addressing via said system backplane serial test bus the addressable shadow port on said selected one of said plurality of boards using a shadow protocol, and further operable to deselect said selected one of said plurality of boards using said shadow protocol, and further operable to select and communicate with another one of said plurality of boards using said shadow protocol, said shadow protocol operable such that any number of such selections and deselections may be made without resetting said system backplane serial bus and the addressable shadow ports on said plurality of boards.