US5485423A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS
Assignee: Cypress Semiconductor Corp
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Filing: 1994-10-11
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Granted: 1996-01-16
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Expires: 2014-10-11
Abstract
Abstract There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
Inventors
- 👤 Yuan Tang
- 👤 Chi Chang
- 👤 Michael A. Van Buskirk
- 👤 Chung K. Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:38
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
84 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low positive pulse voltage to a source region of said EEPROM devices during an entire erase cycle; and simultaneously applying a negative ramp voltage to a control gate of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
Claim 2
Independent Claim
84 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low positive pulse voltage to a source region of said EEPROM devices during an entire erase cycle; and simultaneously applying a negative ramp voltage to a control gate of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
Claim 3
Dependent Claim
19 words
A method as claimed in claim 1, wherein said low positive pulse voltage has a magnitude of +5 volts.
Claim 4
Dependent Claim
39 words
A method as claimed in claim 2, wherein said negative ramp voltage has an initial magnitude of -5 volts and is gradually decreased to the magnitude of -9.5 volts at the rate of approximately -0.09 volts per 10 ms.
Claim 5
Dependent Claim
19 words
A method as claimed in claim 3, wherein said negative ramp voltage remains as -9.5 volts after 500 ms.
Claim 6
Independent Claim
114 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low negative pulse voltage to a control gate of said EEPROM devices during an entire erase cycle; simultaneously applying a positive ramp voltage to a source region of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle; and applying said positive ramp voltage with an initial magnitude of +5 volts and gradually increasing the magnitude to +7.5 volts at the rate of approximately +0.05 volts per 10 ms.
Claim 7
Independent Claim
114 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low negative pulse voltage to a control gate of said EEPROM devices during an entire erase cycle; simultaneously applying a positive ramp voltage to a source region of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle; and applying said positive ramp voltage with an initial magnitude of +5 volts and gradually increasing the magnitude to +7.5 volts at the rate of approximately +0.05 volts per 10 ms.
Claim 8
Dependent Claim
19 words
A method as claimed in claim 5, wherein said low negative pulse voltage has a magnitude of -5 volts.
Claim 9
Dependent Claim
19 words
A method as claimed in claim 5, wherein said positive ramp voltage remains as +7.5 volts after 500 ms.
Claim 10
Independent Claim
114 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low negative pulse voltage to a control gate of said EEPROM devices during an entire erase cycle; simultaneously applying a positive ramp voltage to a source region of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle; and applying said positive ramp voltage with an initial magnitude of +2.5 volts and gradually increasing the magnitude to +4.5 volts at the rate of approximately +0.04 volts per 10 ms.
Claim 11
Independent Claim
114 words
A method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices, said method comprising the steps of: applying a relatively low negative pulse voltage to a control gate of said EEPROM devices during an entire erase cycle; simultaneously applying a positive ramp voltage to a source region of said EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle; and applying said positive ramp voltage with an initial magnitude of +2.5 volts and gradually increasing the magnitude to +4.5 volts at the rate of approximately +0.04 volts per 10 ms.
Claim 12
Dependent Claim
19 words
A method as claimed in claim 8, wherein said low negative pulse voltage has a magnitude of -9.5 volts.
Claim 13
Dependent Claim
19 words
A method as claimed in claim 8, wherein said positive ramp voltage remains at +4.5 volts after 500 ms.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |