Abstract An on-screen display circuit of the interlaced scanning type comprising a vertical counter for counting a horizontal synchronous signal inputted thereto and outputting the counted values as higher-order bits of a vertical address, a 1-bit counter for counting a vertical synchronous signal inputted thereto by one bit and outputting the counted value as a least significant bit of the vertical address, a vertical decoder for decoding output signals from the vertical counter and the 1-bit counter to designate a decoded vertical address, a character decoder for decoding a character address inputted thereto to designate a decoded horizontal address, and a font read only memory for outputting font data in its location corresponding to the decoded vertical address from the vertical decoder and the decoded horizontal address from the character decoder. The vertical decoder designates the vertical address of the font read only memory in response to the least significant bit from the 1-bit counter which is the counted value of the vertical synchronous signal, so that the font data from the font read only memory can be displayed on a screen in an interlaced scanning manner, being divided into odd and even fields of a video signal. Therefore, the present invention has the effect of doubling a resolution.
An on-screen display circuit of the interlaced scanning type comprising: a vertical counter for counting a horizontal synchronous signal inputted thereto and outputting the counted values as higher-order bits of a vertical address; a 1-bit counter for counting a vertical synchronous signal inputted thereto by one bit and outputting the counted value as a least significant bit of the vertical address; a vertical decoder for decoding output signals from said vertical counter and said 1-bit counter to designate a decoded vertical address; a character decoder for decoding a character address inputted thereto to designate a decoded horizontal address; and a font read only memory for outputting font data in its location corresponding to the-decoded vertical address from said vertical decoder and the decoded horizontal address from said character decoder.
Claim 2
Dependent Claim
129 words
An on-screen display circuit of the interlaced scanning type comprising: a vertical counter for counting a horizontal synchronous signal inputted thereto and outputting the counted values as higher-order bits of a vertical address; a 1-bit counter for counting a vertical synchronous signal inputted thereto by one bit and outputting the counted value as a least significant bit of the vertical address; a vertical decoder for decoding output signals from said vertical counter and said 1-bit counter to designate a decoded vertical address; a character decoder for decoding a character address inputted thereto to designate a decoded horizontal address; and a font read only memory for outputting font data in its location corresponding to the-decoded vertical address from said vertical decoder and the decoded horizontal address from said character decoder.
Claim 3
Dependent Claim
89 words
An on-screen display circuit of the interlaced scanning type as set forth in claim 1, wherein said vertical decoder is adapted to designate the decoded vertical address of said font read only memory in response to the least significant bit from said 1-bit counter, said least significant bit being the counted value of the vertical synchronous signal, so that the font data from said font read only memory can be displayed on a screen in an interlaced scanning manner divided into odd and even fields of a video signal.