US5487034A
Expired / Lapsed
US
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Semiconductor memory device and method for writing data therein
Assignee: NEC Electronics Corp
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Filing: 1994-09-19
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Granted: 1996-01-23
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Expires: 2014-09-19
Abstract
Abstract A method for writing data into a memory transistor having a floating gate includes applying a first voltage to a control gate electrode of memory transistor and applying a second voltage to both the source and the drain electrodes of memory transistor, the second voltage being lower than the first voltage. Data is written to the memory transistor by electrons injected into the floating gate due to the F-N tunnel effect. EEPROM comprises a simultaneous-write control circuit for controlling X-address decoder and Y-address decoder so as to simultaneously select all of word lines and all of bit lines, and a source switching circuit for applying a potential equal to the drain potential to the source electrode. All of memory transistors undergo a simultaneous write operation without utilizing a channel current, so that the current consumption can be reduced in the writing operation. Further, the amount of time for pre-erasure writing operation can be reduced for a higher speed in operation of the EEPROM.
Inventors
- 👤 Tatsuro Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:13
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/04; G11C17/00; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/69
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
100 words
A method for writing data into a semiconductor memory device having a semiconductor substrate and a plurality of memory transistors arrayed in rows and columns on a main surface of said substrate, said memory transistors each having source and drain regions, a floating gate and a control gate electrode, said method including applying a first positive voltage to said control gate electrode relative to said semiconductor substrate and applying a second positive voltage lower than the first positive voltage to each of said drain and source regions relative to said semiconductor substrate to thereby inject electrons into said floating gate.
Claim 2
Independent Claim
100 words
A method for writing data into a semiconductor memory device having a semiconductor substrate and a plurality of memory transistors arrayed in rows and columns on a main surface of said substrate, said memory transistors each having source and drain regions, a floating gate and a control gate electrode, said method including applying a first positive voltage to said control gate electrode relative to said semiconductor substrate and applying a second positive voltage lower than the first positive voltage to each of said drain and source regions relative to said semiconductor substrate to thereby inject electrons into said floating gate.
Claim 3
Dependent Claim
39 words
A method for writing data into a semiconductor memory device as defined in claim 1 wherein said applying the first positive voltage and applying the second positive voltage are effected to all of said plurality of memory transistors simultaneously.
Claim 4
Dependent Claim
48 words
A method for writing data into a semiconductor memory device as defined in claim 1 wherein said applying the first positive voltage and said applying the second positive voltage generate an electric field having an intensity not lower than about 10 7 V/cm within said first insulating film.
Claim 5
Dependent Claim
37 words
A method for writing data into a semiconductor memory device as defined in claim 3 wherein the second positive voltage is between about 7 volts and 10 volts when the first positive voltage is about 14 volts.
Claim 6
Dependent Claim
244 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of memory transistors arrayed in rows and columns on said semiconductor substrate, said memory transistors each having a source and a drain regions, a floating gate and a control gate electrode; a word line disposed for each row of said memory transistors and connected to each control gate electrode of corresponding row of said memory transistors; a bit line disposed for each column of said memory transistors and connected to each said drain region of corresponding column of said memory transistors; a source line disposed for each pair of columns of said memory transistors and connected to each said source region of corresponding one of said memory transistors; a word line selection circuit for selecting at least one said word line to apply a first positive voltage thereto relative to said semiconductor substrate; a bit line selection circuit for selecting at least one bit line to apply a second positive voltage thereto relative to said semiconductor substrate, said second voltage being lower than said first voltage; a simultaneous-selection control circuit for controlling said word line selection circuit and said bit line selection circuit to simultaneously select a plurality of said word lines and a plurality of said bit lines; and a switching circuit for applying said second positive voltage to each said source line corresponding to each of the selected bit lines in response to the selective operation of the simultaneous selection control circuit.
Claim 7
Dependent Claim
244 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of memory transistors arrayed in rows and columns on said semiconductor substrate, said memory transistors each having a source and a drain regions, a floating gate and a control gate electrode; a word line disposed for each row of said memory transistors and connected to each control gate electrode of corresponding row of said memory transistors; a bit line disposed for each column of said memory transistors and connected to each said drain region of corresponding column of said memory transistors; a source line disposed for each pair of columns of said memory transistors and connected to each said source region of corresponding one of said memory transistors; a word line selection circuit for selecting at least one said word line to apply a first positive voltage thereto relative to said semiconductor substrate; a bit line selection circuit for selecting at least one bit line to apply a second positive voltage thereto relative to said semiconductor substrate, said second voltage being lower than said first voltage; a simultaneous-selection control circuit for controlling said word line selection circuit and said bit line selection circuit to simultaneously select a plurality of said word lines and a plurality of said bit lines; and a switching circuit for applying said second positive voltage to each said source line corresponding to each of the selected bit lines in response to the selective operation of the simultaneous selection control circuit.
Claim 8
Dependent Claim
27 words
A semiconductor memory device as defined in claim 5 wherein said simultaneous selection circuit simultaneously selects all of said word lines and all of said bit lines.
Claim 9
Dependent Claim
29 words
A semiconductor memory device as defined in claim 5 wherein said simultaneous selection circuit simultaneously selects a block of said word lines and a block of said bit lines.
Claim 10
Dependent Claim
31 words
A semiconductor memory device as defined in claim 5 wherein said second positive voltage is between about 7 volts and 10 volts while said first positive voltage is about 14 volts.
Claim 11
Dependent Claim
232 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of memory transistors arrayed in rows and columns on said semiconductor substrate in a virtual grounding configuration, said memory transistors each having a source and a drain regions, a floating gate and a control gate electrode; a word line disposed for each row of said memory transistors and connected to each control gate electrode of corresponding row of said memory transistors; a first bit line disposed for each column of said memory transistors and connected to each drain region of corresponding column of said memory transistors; a second bit lines disposed for each pair of columns of said memory transistors and connected to each said source region of corresponding pair of said memory transistors; a word line selection circuit for selecting at least one said word line to apply a first positive voltage thereto relative to said semiconductor substrate; a bit line selection circuit for selecting at least one said first bit line and corresponding said second bit line to apply a second positive voltage thereto relative to said semiconductor substrate, said second voltage being lower than said first voltage; a simultaneous-selection control circuit for controlling said word line selection circuit and said bit line selection circuit to simultaneously select a plurality of said word lines and a plurality of combinations of said first bit line and corresponding said second bit line.
Claim 12
Dependent Claim
232 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of memory transistors arrayed in rows and columns on said semiconductor substrate in a virtual grounding configuration, said memory transistors each having a source and a drain regions, a floating gate and a control gate electrode; a word line disposed for each row of said memory transistors and connected to each control gate electrode of corresponding row of said memory transistors; a first bit line disposed for each column of said memory transistors and connected to each drain region of corresponding column of said memory transistors; a second bit lines disposed for each pair of columns of said memory transistors and connected to each said source region of corresponding pair of said memory transistors; a word line selection circuit for selecting at least one said word line to apply a first positive voltage thereto relative to said semiconductor substrate; a bit line selection circuit for selecting at least one said first bit line and corresponding said second bit line to apply a second positive voltage thereto relative to said semiconductor substrate, said second voltage being lower than said first voltage; a simultaneous-selection control circuit for controlling said word line selection circuit and said bit line selection circuit to simultaneously select a plurality of said word lines and a plurality of combinations of said first bit line and corresponding said second bit line.
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| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
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