US5487162A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache lock information feeding system using an address translator
Assignee: Panasonic Holdings Corp
•
Filing: 1994-11-10
•
Granted: 1996-01-23
•
Expires: 2014-11-10
Abstract
Abstract A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.
Inventors
- 👤 Tetsuya Tanaka
- 👤 Takashi Taniguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
243 words
An apparatus for cache lock control, comprising: a cache memory having a plurality of data entries, each of said data entries including at least one data segment for storing data, at least one address segment for storing an address, and at least one cache lock segment for storing cache lock information; and means for controlling updating of said at least one data segment and said at least one address segment in any of the data entries of the cache memory in response to cache lock information in corresponding cache lock segments in said any of the data entries such that data segments and address segments of each of said plurality of data entries are selectively preventable from being overwritten by setting a corresponding cache lock segment, further including: an address translator having a plurality of address entries, each of said address entries including at least a cache locking segment storing cache lock information corresponding to said cache memory; means for selecting one of the data entries of said cache memory; means for updating an address segment and a data segment in a selected data entry of said cache memory; and means for transferring cache lock information to a cache lock segment of the selected data entry of said cache memory from a cache locking segment in a corresponding address entry of said address translator when an address segment and a data segment in the selected data entry of said cache memory are updated.
Claim 2
Independent Claim
243 words
An apparatus for cache lock control, comprising: a cache memory having a plurality of data entries, each of said data entries including at least one data segment for storing data, at least one address segment for storing an address, and at least one cache lock segment for storing cache lock information; and means for controlling updating of said at least one data segment and said at least one address segment in any of the data entries of the cache memory in response to cache lock information in corresponding cache lock segments in said any of the data entries such that data segments and address segments of each of said plurality of data entries are selectively preventable from being overwritten by setting a corresponding cache lock segment, further including: an address translator having a plurality of address entries, each of said address entries including at least a cache locking segment storing cache lock information corresponding to said cache memory; means for selecting one of the data entries of said cache memory; means for updating an address segment and a data segment in a selected data entry of said cache memory; and means for transferring cache lock information to a cache lock segment of the selected data entry of said cache memory from a cache locking segment in a corresponding address entry of said address translator when an address segment and a data segment in the selected data entry of said cache memory are updated.
Claim 3
Independent Claim
310 words
An apparatus for cache lock control, comprising: a cache memory having a plurality of data entries, each of said plurality of data entries being divided into a plurality of segments including: at least one data segment for storing data, at least one address segment for storing an address, and at least one cache lock segment for storing cache lock information; means for controlling updating of said at least one data segment and said at least one address segment in any of the data entries of the cache memory in response to cache lock information in corresponding cache lock segments in said any of the data entries such that data segments and address segments of each of said plurality of data entries are selectively preventable from being overwritten by setting a corresponding cache lock segment therein; an address translator having a plurality of address entries, each of said plurality of address entries divided into a plurality of segments including at least one cache locking segment storing cache lock information; means for selecting one of the data entries of said cache memory; means for updating a data segment and an address segment in a selected data entry of said cache memory; and means for transferring cache lock information to a cache lock segment of the selected data entry of said cache memory from a cache locking segment in a corresponding address entry of said address translator when a data segment and an address segment in the selected data entry of said cache memory are updated; wherein said means for controlling includes: a control register for storing information represented by a cache lock control bit, and means for selectively executing and inhibiting said updating of a data segment and an address segment in said any of the data entries of said cache memory in response to the information stored in the control register.
Claim 4
Independent Claim
310 words
An apparatus for cache lock control, comprising: a cache memory having a plurality of data entries, each of said plurality of data entries being divided into a plurality of segments including: at least one data segment for storing data, at least one address segment for storing an address, and at least one cache lock segment for storing cache lock information; means for controlling updating of said at least one data segment and said at least one address segment in any of the data entries of the cache memory in response to cache lock information in corresponding cache lock segments in said any of the data entries such that data segments and address segments of each of said plurality of data entries are selectively preventable from being overwritten by setting a corresponding cache lock segment therein; an address translator having a plurality of address entries, each of said plurality of address entries divided into a plurality of segments including at least one cache locking segment storing cache lock information; means for selecting one of the data entries of said cache memory; means for updating a data segment and an address segment in a selected data entry of said cache memory; and means for transferring cache lock information to a cache lock segment of the selected data entry of said cache memory from a cache locking segment in a corresponding address entry of said address translator when a data segment and an address segment in the selected data entry of said cache memory are updated; wherein said means for controlling includes: a control register for storing information represented by a cache lock control bit, and means for selectively executing and inhibiting said updating of a data segment and an address segment in said any of the data entries of said cache memory in response to the information stored in the control register.
Claim 5
Dependent Claim
78 words
The apparatus for cache lock control recited in claim 2, wherein said address translator comprises means for translating a virtual address to a physical address of a memory thereby to identify one of a plurality of addresses of the memory for entering data therefrom to one of said data entries of said cache memory, and for providing said cache lock information to said cache lock segment of the said one of said data entries of said cache memory.
References Cited (Backward Citations)
US4638426A
Cited
US5029072A
Cited
US5168568A
Cited
US5297270A
Cited
US5249286A
Cited
US5163143A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |