US5488317A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wired logic functions on FPGA's
Assignee: Texas Instruments Inc
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Filing: 1993-10-22
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Granted: 1996-01-30
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Expires: 2013-10-22
Abstract
Abstract An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).
Inventors
- 👤 William S. Webster
- 👤 David D. Wilmoth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:17
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17788; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/17704
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
187 words
A field programmable logic array having a plurality of logic modules, comprising: a configurable output driver in each of said plurality of logic modules that enables a plurality of output nodes of said plurality of logic modules to be connected together for a wired logic function and that enables each of said plurality of output nodes to be connected separately to one of a plurality of output lines, wherein said configurable output driver comprises: a p-channel driver transistor connected to one of said output nodes: a n-channel driver transistor connected between said one of said output nodes and ground; and driver disable circuitry operable to disable said p-channel driver transistor when said plurality of output nodes are to be connected together, said driver disable circuitry comprising: a first programmable element connected between said driver disable circuitry and logic signal in order to provide a high logic signal to a gate of said p-channel driver transistor; and a second programmable element connected between said driver disable circuitry and a second logic signal in order to supply an internal logic signal to said gate of said p-channel driver transistor.
Claim 2
Dependent Claim
187 words
A field programmable logic array having a plurality of logic modules, comprising: a configurable output driver in each of said plurality of logic modules that enables a plurality of output nodes of said plurality of logic modules to be connected together for a wired logic function and that enables each of said plurality of output nodes to be connected separately to one of a plurality of output lines, wherein said configurable output driver comprises: a p-channel driver transistor connected to one of said output nodes: a n-channel driver transistor connected between said one of said output nodes and ground; and driver disable circuitry operable to disable said p-channel driver transistor when said plurality of output nodes are to be connected together, said driver disable circuitry comprising: a first programmable element connected between said driver disable circuitry and logic signal in order to provide a high logic signal to a gate of said p-channel driver transistor; and a second programmable element connected between said driver disable circuitry and a second logic signal in order to supply an internal logic signal to said gate of said p-channel driver transistor.
Claim 3
Dependent Claim
26 words
The FPGA of claim 1, wherein said driver disable circuitry comprises a p-channel transistor operable to interrupt a supply voltage from reaching said p-channel driver transistor.
Claim 4
Dependent Claim
48 words
The FPGA of claim 1, wherein said driver disable circuitry comprises signal interrupt circuitry operable to interrupt an internal logic module signal from reaching a gate of said p-channel driver transistor or operable to supply said internal logic module signal to said gate of said p-channel driver transistor.
Claim 5
Dependent Claim
48 words
The FPGA of claim 1, wherein said driver disable circuitry further comprises a third programmable element connected between said driver disable circuitry and a control signal that determines whether to provide said high logic signal or said internal logic signal to said gate of said p-channel driver transistor.
Claim 6
Dependent Claim
15 words
The FPGA of claim 4, wherein said first, second, and third programmable elements comprise antifuses.
Claim 7
Dependent Claim
55 words
The FPGA of claim 1, wherein said plurality of logic modules further comprise: a. a p-channel pull-up transistor connected between a supply voltage and said one of said output nodes; and b. pull-up circuitry operable to selectively connect a gate of said p-channel pull-up transistor to a logic low signal or a logic high signal.
Claim 8
Dependent Claim
41 words
The FPGA of claim 1, further comprising: a. at least one interconnect line for connecting said output nodes when said plurality of output nodes are to be connected together; and b. a senseamp connected to said at least one interconnect line.
Claim 9
Dependent Claim
14 words
The FPGA of claim 7, wherein said output nodes are arranged in a row.
Claim 10
Dependent Claim
14 words
The FPGA of claim 7, wherein said output nodes are arranged in a column.
Claim 11
Dependent Claim
14 words
The FPGA of claim 7, wherein said output nodes are arranged in a randomly.
Claim 12
Independent Claim
124 words
A method of configuring the output drivers of at least two logic modules of a FPGA comprising the steps of: a. providing a first programmable element operable to disable current conduction in a p-channel driver transistor if a first and second output of said at least two logic modules are to be connected together; b. providing a second programmable element operable to provide an internal logic signal to a gate of said p-channel driver transistor if said first and second outputs are to be separately connected to first and second output lines, respectively; c. selectively blowing one of said first and second programmable elements; and d. providing said internal logic signal to an n-channel driver transistor connected between said n-channel driver transistor and ground.
Claim 13
Independent Claim
124 words
A method of configuring the output drivers of at least two logic modules of a FPGA comprising the steps of: a. providing a first programmable element operable to disable current conduction in a p-channel driver transistor if a first and second output of said at least two logic modules are to be connected together; b. providing a second programmable element operable to provide an internal logic signal to a gate of said p-channel driver transistor if said first and second outputs are to be separately connected to first and second output lines, respectively; c. selectively blowing one of said first and second programmable elements; and d. providing said internal logic signal to an n-channel driver transistor connected between said n-channel driver transistor and ground.
Claim 14
Dependent Claim
39 words
The method of claim 11, further comprising the step of connecting said first and second outputs of said at least two logic modules to a first interconnect line when said first and second outputs are to be connected together.
Claim 15
Dependent Claim
19 words
The method of claim 12, further comprising the step of providing a senseamp connected to said first interconnect line.
Claim 16
Dependent Claim
31 words
The method of claim 11, further comprising the step of providing a pull-up transistor for said first and second outputs when said first and second outputs are to be connected together.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |