US5489870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage booster circuit
Assignee: Sony Corp
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Filing: 1994-03-17
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Granted: 1996-02-06
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Expires: 2014-03-17
Abstract
Abstract A booster circuit which can cancel the back bias effect, can prevent the increase of the surface area of the circuit and the power consumption, prevent the complication of the clock generation circuit, and prevent lowering of the current capability, wherein a boosting stage is constituted by forming an nMOS transistor NT for carrying the charges and nMOS transistor NTB for transferring the voltage inside a p-well formed inside an n-well which is formed on a p-type semiconductor substrate and biased to a predetermined potential, constituted so that the source voltage of the nMOS transistor NT for carrying the charges which rise at the boosting is transferred via the nMOS transistor NTB for transferring the voltage to the substrate, that is, the p-well, whereby the back bias effect is suppressed.
Inventors
- 👤 Hideki Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:55
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; H02M3/078
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
90 words
A booster circuit comprising: a first transistor operatively connecting a first node and a second node which are connected to a boosting element and which are complementarily boosted and a second transistor which operatively connects the second node and a substrate well of said first transistor, said second transistor having a substrate well, said first node being connected to a gate of said first transistor and a gate of said second transistor, and said substrate well of said first transistor and said substrate well of said second transistor being connected.
Claim 2
Dependent Claim
90 words
A booster circuit comprising: a first transistor operatively connecting a first node and a second node which are connected to a boosting element and which are complementarily boosted and a second transistor which operatively connects the second node and a substrate well of said first transistor, said second transistor having a substrate well, said first node being connected to a gate of said first transistor and a gate of said second transistor, and said substrate well of said first transistor and said substrate well of said second transistor being connected.
Claim 3
Dependent Claim
95 words
A booster circuit comprising: a first transistor operatively connecting a first node and a second node which are connected to a boosting element and which are complementarily boosted and a second transistor which operatively connects said first node and a substrate well of said first transistor, said second transistor having a substrate well, said first node being connected to a gate of said first transistor, said second node being connected to a gate of said second transistor, and said substrate well of said first transistor and said substrate well of said second transistor being connected.
Claim 4
Dependent Claim
95 words
A booster circuit comprising: a first transistor operatively connecting a first node and a second node which are connected to a boosting element and which are complementarily boosted and a second transistor which operatively connects said first node and a substrate well of said first transistor, said second transistor having a substrate well, said first node being connected to a gate of said first transistor, said second node being connected to a gate of said second transistor, and said substrate well of said first transistor and said substrate well of said second transistor being connected.
Claim 5
Dependent Claim
129 words
A booster circuit comprising: a first substrate well comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well comprising a second conductivity type semiconductor region formed in the first substrate well; first, second, third, and fourth element side diffusion layers comprising at least three first conductivity type element side diffusion layers formed inside the second substrate well; a first gate electrode formed on a space between said first and second element side diffusion layers; and a second gate electrode formed on the space between said third and second element side diffusion layers, said first element side diffusion layer being connected to said first and second gate electrodes, and said fourth element side diffusion layer being connected to said third element side diffusion layer.
Claim 6
Dependent Claim
129 words
A booster circuit comprising: a first substrate well comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well comprising a second conductivity type semiconductor region formed in the first substrate well; first, second, third, and fourth element side diffusion layers comprising at least three first conductivity type element side diffusion layers formed inside the second substrate well; a first gate electrode formed on a space between said first and second element side diffusion layers; and a second gate electrode formed on the space between said third and second element side diffusion layers, said first element side diffusion layer being connected to said first and second gate electrodes, and said fourth element side diffusion layer being connected to said third element side diffusion layer.
Claim 7
Dependent Claim
167 words
A booster circuit comprising: a first substrate well comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well comprising a second conductivity type semiconductor region formed in the first substrate well; first, second, third, and fourth element side diffusion layers comprising at least three first conductivity type element side diffusion layers formed inside the second substrate well; a fifth element side diffusion layer comprising a second conductivity type element side diffusion layer formed inside the second substrate well; a first gate electrode formed on a space between said first and second element side diffusion layers; and a second gate electrode formed on the space between said third and fourth element side diffusion layers, said first element side diffusion layer being connected to said third element side diffusion layer and first gate electrode, said second element side diffusion layer being connected to said second gate electrode, and said fourth element side diffusion layer being connected to said fifth element side diffusion layer.
Claim 8
Dependent Claim
167 words
A booster circuit comprising: a first substrate well comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well comprising a second conductivity type semiconductor region formed in the first substrate well; first, second, third, and fourth element side diffusion layers comprising at least three first conductivity type element side diffusion layers formed inside the second substrate well; a fifth element side diffusion layer comprising a second conductivity type element side diffusion layer formed inside the second substrate well; a first gate electrode formed on a space between said first and second element side diffusion layers; and a second gate electrode formed on the space between said third and fourth element side diffusion layers, said first element side diffusion layer being connected to said third element side diffusion layer and first gate electrode, said second element side diffusion layer being connected to said second gate electrode, and said fourth element side diffusion layer being connected to said fifth element side diffusion layer.
Claim 9
Dependent Claim
25 words
A booster circuit as set forth in claim 3, wherein said first conductivity type comprises an n-type and said second conductivity type comprises a p-type.
Claim 10
Dependent Claim
25 words
A booster circuit as set forth in claim 4, wherein said first conductivity type comprises an n-type and said second conductivity type comprises a p-type.
References Cited (Backward Citations)
US4384218A
Cited
US5081371A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |