US5491702A
Expired / Lapsed
US
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Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word
Assignee: ARM Finance Overseas Ltd
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Filing: 1992-07-22
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Granted: 1996-02-13
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Expires: 2012-07-22
Abstract
Abstract An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1"s or by syndromes that contain exactly five "1"s in which bits 0-3 or 4-7 of the syndrome are all "1." Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1." All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that contain an even number of "1"s (i.e., an even number of "1"s). Three-bit errors within a nibble are indicated by syndromes that contain five "1"s in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all "1." Four-bit errors within a nibble are indicated by syndromes that contain four "1"s. In another embodiment of the invention, 25 bits of data word are protected by 7 check bits yielding 7-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1" s except single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1". Two-bit errors are indicated by syndromes that contain an even number of "1"s, and three-bit errors within a nibble are indicated by syndromes that contain five "1"s or seven "1"s. Four-bit errors within a nibble are indicated by syndromes that contain four "1"s or six "1"s.
Inventors
- 👤 John R. Kinsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:23
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1028; H; H03; H03M; H03M13/00; H03M13/47; H03M13/51
Claims Analysis
Total Claims: 127
Claim 1
Independent Claim
113 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple-bit syndrome from the block of data; and three-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a three-bit error within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors, wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 2
Independent Claim
113 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple-bit syndrome from the block of data; and three-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a three-bit error within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors, wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 3
Dependent Claim
30 words
The apparatus according to claim 1 further comprising one-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of only one-bit errors within the block of data.
Claim 4
Dependent Claim
54 words
The apparatus according to claim 1 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the more-than-three-ones detecting means comprises three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of exactly three ones in the first four-bit portion of the syndrome.
Claim 5
Dependent Claim
39 words
The apparatus according to claim 3 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 6
Dependent Claim
52 words
The apparatus according to claim 1 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the more-than-three-ones detecting means comprises three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 7
Dependent Claim
38 words
The apparatus according to claim 5 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 8
Dependent Claim
35 words
The apparatus according to claim 5 wherein the more-than-three-ones detecting means comprises three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 9
Dependent Claim
38 words
The apparatus according to claim 7 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 10
Dependent Claim
56 words
The apparatus according to claim 1 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 11
Dependent Claim
56 words
The apparatus according to claim 9 wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 12
Dependent Claim
38 words
The apparatus according to claim 10 wherein the more-than-three-ones detecting means comprises first three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of exactly three ones in the first four-bit portion of the syndrome.
Claim 13
Dependent Claim
40 words
The apparatus according to claim 11 wherein the more-than-three-ones detecting means further comprises first three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 14
Dependent Claim
67 words
The apparatus according to claim 12 wherein the more-than-three-ones detecting means further comprises: second three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of exactly three ones in the second four-bit portion of the syndrome; and second ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the first four-bit portion of the syndrome.
Claim 15
Dependent Claim
40 words
The apparatus according to claim 1 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly five ones.
Claim 16
Dependent Claim
56 words
The apparatus according to claim 14 wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 17
Dependent Claim
37 words
The apparatus according to claim 15 wherein the more-than-three-ones detecting means comprises three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 18
Dependent Claim
38 words
The apparatus according to claim 16 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 19
Dependent Claim
35 words
The apparatus according to claim 15 wherein the more-than-three-ones detecting means comprises three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 20
Dependent Claim
38 words
The apparatus according to claim 18 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 21
Dependent Claim
37 words
The apparatus according to claim 19 wherein the more-than-three-ones detecting means comprises three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 22
Dependent Claim
38 words
The apparatus according to claim 20 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 23
Dependent Claim
25 words
The apparatus according to claim 21 wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly seven ones.
Claim 24
Dependent Claim
34 words
The apparatus according to claim 1 wherein the block of data comprises a plurality of check bits interspersed throughout the block of data and not grouped together and appended to the block of data.
Claim 25
Independent Claim
109 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple-bit syndrome from the block of data; and four-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a four-bit error within a four bit group of data bits within the block of data, the four bit error indicating means comprising: even-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of an even number of ones in the syndrome; and error signalling means, coupled to the even-ones detecting means, for providing an error signal when the syndrome contains an even number of ones.
Claim 26
Independent Claim
109 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple-bit syndrome from the block of data; and four-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a four-bit error within a four bit group of data bits within the block of data, the four bit error indicating means comprising: even-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of an even number of ones in the syndrome; and error signalling means, coupled to the even-ones detecting means, for providing an error signal when the syndrome contains an even number of ones.
Claim 27
Dependent Claim
30 words
The apparatus according to claim 24 further comprising one-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of only one-bit errors within the block of data.
Claim 28
Dependent Claim
13 words
The apparatus according to claim 25 wherein the syndrome contains exactly eight bits.
Claim 29
Dependent Claim
13 words
The apparatus according to claim 25 wherein the syndrome contains exactly seven bits.
Claim 30
Dependent Claim
25 words
The apparatus according to claim 27 wherein the four-bit-error indicating means indicates the occurrence of a four-bit error when the syndrome contains exactly six ones.
Claim 31
Dependent Claim
25 words
The apparatus according to claim 24 wherein the four-bit-error indicating means indicates the occurrence of a four-bit error when the syndrome contains exactly four ones.
Claim 32
Dependent Claim
34 words
The apparatus according to claim 24 wherein the block of data comprises a plurality of check bits interspersed throughout the block of data and not grouped together and appended to the block of data.
Claim 33
Independent Claim
147 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple bit syndrome from the block of data; three-bit error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a three-bit error within any four bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors; and four-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a four-bit error within any four-bit group or data bits within the block of data, wherein the four-bit-error indicating means comprises: even-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of an even number of ones in the syndrome; and error signalling means, coupled to the even-ones detecting means, for providing an error signal when the syndrome contains an even number of ones.
Claim 34
Independent Claim
147 words
An apparatus for detecting data errors in a block of data comprising: syndrome calculating means for calculating a multiple bit syndrome from the block of data; three-bit error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a three-bit error within any four bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors; and four-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of a four-bit error within any four-bit group or data bits within the block of data, wherein the four-bit-error indicating means comprises: even-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of an even number of ones in the syndrome; and error signalling means, coupled to the even-ones detecting means, for providing an error signal when the syndrome contains an even number of ones.
Claim 35
Dependent Claim
25 words
The apparatus according to claim 31 wherein the four-bit-error indicating means indicates the occurrence of a four-bit error when the syndrome contains exactly four ones.
Claim 36
Dependent Claim
56 words
The apparatus according to claim 31 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 37
Dependent Claim
56 words
The apparatus according to claim 33 wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 38
Dependent Claim
37 words
The apparatus according to claim 34 wherein the more-than-three-ones detecting means comprises three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurence of exactly three ones in the first four-bit portion of the syndrome.
Claim 39
Dependent Claim
39 words
The apparatus according to claim 35 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 40
Dependent Claim
29 words
The apparatus according to claim 36 further comprising one-bit-error indicating means, coupled to the syndrome calculating means, for indicating every occurrence of one-bit errors within the block of data.
Claim 41
Dependent Claim
22 words
The apparatus according to claim 37 wherein the one-bit-error indicating means provides an error signal when the syndrome contains exactly one one.
Claim 42
Dependent Claim
22 words
The apparatus according to claim 37 wherein the one-bit-error indicating means provides an error signal when the syndrome contains exactly three ones.
Claim 43
Dependent Claim
36 words
The apparatus according to claim 37 wherein the one-bit-error indicating means provides an error signal when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 44
Dependent Claim
51 words
The apparatus according to claim 37 wherein the one-bit-error indicating means provides an error signal when the syndrome contains exactly one one, when the syndrome contains exactly three ones, and when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 45
Dependent Claim
40 words
The apparatus according to claim 31 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly five ones.
Claim 46
Dependent Claim
56 words
The apparatus according to claim 42 wherein the three-bit-error indicating means comprises: more-than-three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of more than three ones in the syndrome; and error signalling means, coupled to the more-than-three-ones detecting means, for providing an error signal when the syndrome contains more than three ones.
Claim 47
Dependent Claim
37 words
The apparatus according to claim 43 wherein the more-than-three-ones detecting means comprises three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 48
Dependent Claim
38 words
The apparatus according to claim 44 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 49
Dependent Claim
35 words
The apparatus according to claim 43 wherein the more-than-three-ones detecting means comprises three-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 50
Dependent Claim
38 words
The apparatus according to claim 46 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 51
Dependent Claim
37 words
The apparatus according to claim 47 wherein the more-than-three-ones detecting means comprises three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 52
Dependent Claim
38 words
The apparatus according to claim 48 wherein the more-than-three-ones detecting means further comprises ones detecting means, coupled to the syndrome calculating means, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 53
Dependent Claim
25 words
The apparatus according to claim 49 wherein the three-bit-error indicating means indicates the occurrence of a three-bit error when the syndrome contains exactly seven ones.
Claim 54
Dependent Claim
34 words
The apparatus according to claim 31 wherein the block of data comprises a plurality of check bits interspersed throughout the block of data and not grouped together and appended to the block of data.
Claim 55
Independent Claim
323 words
An apparatus for detecting data errors in a sixty-four bit block of data comprising: syndrome calculating means for calculating an eight bit syndrome from the block of data, the syndrome including a first four-bit portion and a second four-bit portion; a first three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of exactly three ones in the first four-bit portion of the syndrome; a second three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of exactly three ones in the second four-bit portion of the syndrome; a first ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of one or more ones in the first four bit portion of the syndrome; a second ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of one or more ones in the second four-bit portion of the syndrome; even ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating means, coupled to the first three ones detecting means, to the second three ones detecting means, to the first ones detecting means, to the second ones detecting means, and to the odd ones detecting means, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating means, coupled to the first three-ones detecting means, to the second three-ones detecting means, to the first ones detecting means, to the second ones detecting means, and to the even ones detecting means, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors.
Claim 56
Independent Claim
323 words
An apparatus for detecting data errors in a sixty-four bit block of data comprising: syndrome calculating means for calculating an eight bit syndrome from the block of data, the syndrome including a first four-bit portion and a second four-bit portion; a first three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of exactly three ones in the first four-bit portion of the syndrome; a second three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of exactly three ones in the second four-bit portion of the syndrome; a first ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of one or more ones in the first four bit portion of the syndrome; a second ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of one or more ones in the second four-bit portion of the syndrome; even ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating means, coupled to the first three ones detecting means, to the second three ones detecting means, to the first ones detecting means, to the second ones detecting means, and to the odd ones detecting means, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating means, coupled to the first three-ones detecting means, to the second three-ones detecting means, to the first ones detecting means, to the second ones detecting means, and to the even ones detecting means, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors.
Claim 57
Dependent Claim
47 words
The apparatus according to claim 52 wherein the uncorrectable error indicating means provides the uncorrectable-error signal when the syndrome contains an even number of ones and when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 58
Dependent Claim
51 words
The apparatus according to claim 52 wherein the one-bit-error indicating means provides the one-bit-error signal when the syndrome contains exactly one one, when the syndrome contains exactly three ones, and when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 59
Dependent Claim
34 words
The apparatus according to claim 52 wherein the block of data comprises a plurality of check bits interspersed throughout the block of data and not grouped together and appended to the block of data.
Claim 60
Independent Claim
305 words
An apparatus for detecting data errors in a twenty-five bit block of data comprising: syndrome calculating means for calculating a seven-bit syndrome from the block of data, the syndrome including a four-bit portion and a three-bit portion; three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of three ones in the three-bit portion of the syndrome; first ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of at least one one in the four-bit portion of the syndrome; three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of three or more ones in the four-bit portion of the syndrome; second ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of at least one one in the three-bit portion of the syndrome; even ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating means, coupled to the three ones detecting means, to the first ones detecting means, to the three-or-more-ones detecting means, to the second ones detecting means, and to the odd ones detecting means, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating means, coupled to the three-ones detecting means, to the first ones detecting means, to the three-or-more-ones detecting means, to the second ones detecting means, and to the even ones detecting means, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three bit errors from one-bit errors.
Claim 61
Independent Claim
305 words
An apparatus for detecting data errors in a twenty-five bit block of data comprising: syndrome calculating means for calculating a seven-bit syndrome from the block of data, the syndrome including a four-bit portion and a three-bit portion; three-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of three ones in the three-bit portion of the syndrome; first ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of at least one one in the four-bit portion of the syndrome; three-or-more-ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of three or more ones in the four-bit portion of the syndrome; second ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of at least one one in the three-bit portion of the syndrome; even ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting means, coupled to the syndrome calculating means, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating means, coupled to the three ones detecting means, to the first ones detecting means, to the three-or-more-ones detecting means, to the second ones detecting means, and to the odd ones detecting means, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating means, coupled to the three-ones detecting means, to the first ones detecting means, to the three-or-more-ones detecting means, to the second ones detecting means, and to the even ones detecting means, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three bit errors from one-bit errors.
Claim 62
Dependent Claim
38 words
The apparatus according to claim 56 wherein the uncorrectable error indicating means provides the uncorrectable-error signal when the syndrome contains an even number of ones and when the syndrome contains an odd number of ones greater than three.
Claim 63
Dependent Claim
27 words
The apparatus according to claim 57 wherein the uncorrectable error indicating means provides the uncorrectable-error signal when the syndrome contains exactly five ones and exactly seven ones.
Claim 64
Dependent Claim
27 words
The apparatus according to claim 56 wherein the one-bit-error indicating means provides the one-bit-error signal when the syndrome contains an odd number of ones less than five.
Claim 65
Dependent Claim
26 words
The apparatus according to claim 59 wherein the one-bit-error indicating means provides the one-bit-error signal when the syndrome contains exactly one one and exactly three ones.
Claim 66
Dependent Claim
34 words
The apparatus according to claim 56 wherein the block of data comprises a plurality of check bits interspersed throughout the block of data and not grouped together and appended to the block of data.
Claim 67
Independent Claim
125 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple-bit syndrome from the block of data; and three-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a three-bit error within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors, wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 68
Independent Claim
125 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple-bit syndrome from the block of data; and three-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a three-bit error within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors, wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 69
Dependent Claim
30 words
The apparatus according to claim 62 further comprising one-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of only one-bit errors within the block of data.
Claim 70
Dependent Claim
54 words
The apparatus according to claim 63 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the more-than-three-ones detecting circuitry comprises three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of exactly three ones in the first four-bit portion of the syndrome.
Claim 71
Dependent Claim
39 words
The apparatus according to claim 64 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 72
Dependent Claim
52 words
The apparatus according to claim 62 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the more-than-three-ones detecting circuitry comprises three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 73
Dependent Claim
38 words
The apparatus according to claim 60 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 74
Dependent Claim
35 words
The apparatus according to claim 60 wherein the more-than-three-ones detecting circuitry comprises three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 75
Dependent Claim
38 words
The apparatus according to claim 68 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 76
Dependent Claim
56 words
The apparatus according to claim 69 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 77
Dependent Claim
56 words
The apparatus according to claim 70 wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 78
Dependent Claim
38 words
The apparatus according to claim 71 wherein the more-than-three-ones detecting circuitry comprises first three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of exactly three ones in the first four-bit portion of the syndrome.
Claim 79
Dependent Claim
40 words
The apparatus according to claim 72 wherein the more-than-three-ones detecting circuitry further comprises first ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 80
Dependent Claim
67 words
The apparatus according to claim 73 wherein the more-than-three-ones detecting circuitry further comprises: second three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of exactly three ones in the second four-bit portion of the syndrome; and second ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the first four-bit portion of the syndrome.
Claim 81
Dependent Claim
40 words
The apparatus according to claim 69 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly five ones.
Claim 82
Dependent Claim
56 words
The apparatus according to claim 75 wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 83
Dependent Claim
37 words
The apparatus according to claim 72 wherein the more-than-three-ones detecting circuitry comprises three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 84
Dependent Claim
38 words
The apparatus according to claim 77 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 85
Dependent Claim
35 words
The apparatus according to claim 76 wherein the more-than-three-ones detecting circuitry comprises three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 86
Dependent Claim
38 words
The apparatus according to claim 79 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 87
Dependent Claim
37 words
The apparatus according to claim 80 wherein the more-than-three-ones detecting circuitry comprises three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 88
Dependent Claim
38 words
The apparatus according to claim 81 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 89
Dependent Claim
25 words
The apparatus according to claim 82 wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly seven ones.
Claim 90
Independent Claim
121 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple-bit syndrome from the block of data; and four-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a four-bit error within a four bit group of data bits within the block of data, the four bit error indicating circuitry comprising: even-ones detecting circuitry, coupled to the syndrome calculating circitry, for detecting the occurrence of an even number of ones in the syndrome; and error signalling circuitry, coupled to the even-ones detecting circuitry, for providing an error signal when the syndrome contains an even number of ones.
Claim 91
Independent Claim
121 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple-bit syndrome from the block of data; and four-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a four-bit error within a four bit group of data bits within the block of data, the four bit error indicating circuitry comprising: even-ones detecting circuitry, coupled to the syndrome calculating circitry, for detecting the occurrence of an even number of ones in the syndrome; and error signalling circuitry, coupled to the even-ones detecting circuitry, for providing an error signal when the syndrome contains an even number of ones.
Claim 92
Dependent Claim
30 words
The apparatus according to claim 84 further comprising one-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of only one-bit errors within the block of data.
Claim 93
Dependent Claim
25 words
The apparatus according to claim 84 wherein the four-bit-error indicating circuitry indicates the occurrence of a four-bit error when the syndrome contains exactly four ones.
Claim 94
Dependent Claim
13 words
The apparatus according to claim 85 wherein the syndrome contains exactly eight bits.
Claim 95
Dependent Claim
13 words
The apparatus according to claim 85 wherein the syndrome contains exactly seven bits.
Claim 96
Dependent Claim
25 words
The apparatus according to claim 88 wherein the four-bit-error indicating circuitry indicates the occurrence of a four-bit error when the syndrome contains exactly six ones.
Claim 97
Independent Claim
159 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple bit syndrome from the block of data; three-bit error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a three-bit error within any four bit group of data bits within the block of data and distinquishing all three-bit errors from one-bit errors; and four-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a four-bit error within any four-bit group of data bits within the block of data, wherein the four-bit-error indicating circuitry comprises: even-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of an even number of ones in the syndrome; and error signalling circuitry, coupled to the even-ones detecting circuitry, for providing an error signal when the syndrome contains an even number of ones.
Claim 98
Independent Claim
159 words
An apparatus for detecting data errors in a block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a multiple bit syndrome from the block of data; three-bit error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a three-bit error within any four bit group of data bits within the block of data and distinquishing all three-bit errors from one-bit errors; and four-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of a four-bit error within any four-bit group of data bits within the block of data, wherein the four-bit-error indicating circuitry comprises: even-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of an even number of ones in the syndrome; and error signalling circuitry, coupled to the even-ones detecting circuitry, for providing an error signal when the syndrome contains an even number of ones.
Claim 99
Dependent Claim
25 words
The apparatus according to claim 90 wherein the four-bit-error indicating circuitry indicates the occurrence of a four-bit error when the syndrome contains exactly four ones.
Claim 100
Dependent Claim
56 words
The apparatus according to claim 90 wherein the syndrome comprises eight bits including a first four-bit portion and a second four-bit portion, and wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 101
Dependent Claim
56 words
The apparatus according to claim 92 wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 102
Dependent Claim
37 words
The apparatus according to claim 93 wherein the more-than-three-ones detecting circuitry comprises three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of exactly three ones in the first four-bit portion of the syndrome.
Claim 103
Dependent Claim
39 words
The apparatus according to claim 94 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the second four-bit portion of the syndrome.
Claim 104
Dependent Claim
29 words
The apparatus according to claim 95 further comprising one-bit-error indicating circuitry, coupled to the syndrome calculating circuitry, for indicating every occurrence of one-bit errors within the block of data.
Claim 105
Dependent Claim
22 words
The apparatus according to claim 96 wherein the one-bit-error indicating circuitry provides an error signal when the syndrome contains exactly one one.
Claim 106
Dependent Claim
22 words
The apparatus according to claim 96 wherein the one-bit-error indicating circuitry provides an error signal when the syndrome contains exactly three ones.
Claim 107
Dependent Claim
36 words
The apparatus according to claim 96 wherein the one-bit-error indicating circuitry provides an error signal when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 108
Dependent Claim
51 words
The apparatus according to claim 96 wherein the one-bit-error indicating circuitry provides an error signal when the syndrome contains exactly one one, when the syndrome contains exactly three ones, and when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 109
Dependent Claim
40 words
The apparatus according to claim 90 wherein the syndrome comprises seven bits including a four-bit portion and a three-bit portion, and wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly five ones.
Claim 110
Dependent Claim
56 words
The apparatus according to claim 101 wherein the three-bit-error indicating circuitry comprises: more-than-three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of more than three ones in the syndrome; and error signalling circuitry, coupled to the more-than-three-ones detecting circuitry, for providing an error signal when the syndrome contains more than three ones.
Claim 111
Dependent Claim
37 words
The apparatus according to claim 102 wherein the more-than-three-ones detecting circuitry comprises three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 112
Dependent Claim
38 words
The apparatus according to claim 103 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 113
Dependent Claim
35 words
The apparatus according to claim 102 wherein the more-than-three-ones detecting circuitry comprises three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three ones in the three-bit portion of the syndrome.
Claim 114
Dependent Claim
38 words
The apparatus according to claim 105 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the four-bit portion of the syndrome.
Claim 115
Dependent Claim
37 words
The apparatus according to claim 106 wherein the more-than-three-ones detecting circuitry comprises three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of three or more ones in the four-bit portion of the syndrome.
Claim 116
Dependent Claim
38 words
The apparatus according to claim 107 wherein the more-than-three-ones detecting circuitry further comprises ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting the occurrence of at least one one in the three-bit portion of the syndrome.
Claim 117
Dependent Claim
25 words
The apparatus according to claim 108 wherein the three-bit-error indicating circuitry indicates the occurrence of a three-bit error when the syndrome contains exactly seven ones.
Claim 118
Independent Claim
335 words
An apparatus for detecting data errors in a sixty-four bit block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating an eight bit syndrome from the block of data, the syndrome including a first four-bit portion and a second four-bit portion; a first three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of exactly three ones in the first four-bit portion of the syndrome; a second three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of exactly three ones in the second four-bit portion of the syndrome; a first ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of one or more ones in the first four bit portion of the syndrome; a second ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of one or more ones in the second four-bit portion of the syndrome; even ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating circuitry, coupled to the first three ones detecting circuitry, to the second three ones detecting circuitry, to the first ones detecting circuitry, to the second ones detecting circuitry, and to the odd ones detecting circuitry, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating circuitry, coupled to the first three-ones detecting circuitry, to the second three-ones detecting circuitry, to the first ones detecting circuitry, to the second ones detecting circuitry, and to the even ones detecting circuitry, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors.
Claim 119
Independent Claim
335 words
An apparatus for detecting data errors in a sixty-four bit block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating an eight bit syndrome from the block of data, the syndrome including a first four-bit portion and a second four-bit portion; a first three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of exactly three ones in the first four-bit portion of the syndrome; a second three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of exactly three ones in the second four-bit portion of the syndrome; a first ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of one or more ones in the first four bit portion of the syndrome; a second ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of one or more ones in the second four-bit portion of the syndrome; even ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating circuitry, coupled to the first three ones detecting circuitry, to the second three ones detecting circuitry, to the first ones detecting circuitry, to the second ones detecting circuitry, and to the odd ones detecting circuitry, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating circuitry, coupled to the first three-ones detecting circuitry, to the second three-ones detecting circuitry, to the first ones detecting circuitry, to the second ones detecting circuitry, and to the even ones detecting circuitry, for providing an uncorrectable-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three-bit errors from one-bit errors.
Claim 120
Dependent Claim
47 words
The apparatus according to claim 110 wherein the uncorrectable error indicating circuitry provides the uncorrectable-error signal when the syndrome contains an even number of ones and when the syndrome contains exactly five ones and neither the first four-bit portion nor the second four-bit portion contain four ones.
Claim 121
Dependent Claim
51 words
The apparatus according to claim 110 wherein the one-bit-error indicating circuitry provides the one-bit-error signal when the syndrome contains exactly one one, when the syndrome contains exactly three ones, and when the syndrome contains exactly five ones and either the first four-bit portion or the second four-bit portion contains four ones.
Claim 122
Independent Claim
317 words
An apparatus for detecting data errors in a twenty-five bit block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a seven-bit syndrome from the block of data, the syndrome including a four-bit portion and a three-bit portion; three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of three ones in the three-bit portion of the syndrome; first ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of at least one one in the four-bit portion of the syndrome; three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of three or more ones in the four-bit portion of the syndrome; second ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of at least one one in the three-bit portion of the syndrome; even ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating circuitry, coupled to the three ones detecting circuitry, to the first ones detecting circuitry, to the three-or-more-ones detecting circuitry, to the second ones detecting circuitry, and to the odd ones detecting circuitry, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating circuitry, coupled to the three-ones detecting circuitry, to the first ones detecting circuitry, to the three-or-more-ones detecting circuitry, to the second ones detecting circuitry, and to the even ones detecting circuitry, for providing an uncorrectabie-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three bit errors from one-bit errors.
Claim 123
Independent Claim
317 words
An apparatus for detecting data errors in a twenty-five bit block of data having a plurality of check bits interspersed throughout the block of data comprising: syndrome calculating circuitry for calculating a seven-bit syndrome from the block of data, the syndrome including a four-bit portion and a three-bit portion; three-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of three ones in the three-bit portion of the syndrome; first ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of at least one one in the four-bit portion of the syndrome; three-or-more-ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of three or more ones in the four-bit portion of the syndrome; second ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of at least one one in the three-bit portion of the syndrome; even ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an even number of ones in the syndrome; odd ones detecting circuitry, coupled to the syndrome calculating circuitry, for detecting an occurrence of an odd number of ones in the syndrome; one-bit-error indicating circuitry, coupled to the three ones detecting circuitry, to the first ones detecting circuitry, to the three-or-more-ones detecting circuitry, to the second ones detecting circuitry, and to the odd ones detecting circuitry, for providing a one-bit-error signal indicating an occurrence of one-bit errors within the block of data; and uncorrectable error indicating circuitry, coupled to the three-ones detecting circuitry, to the first ones detecting circuitry, to the three-or-more-ones detecting circuitry, to the second ones detecting circuitry, and to the even ones detecting circuitry, for providing an uncorrectabie-error signal indicating every occurrence of two-bit errors and three-bit and four-bit errors within a four-bit group of data bits within the block of data and distinguishing all three bit errors from one-bit errors.
Claim 124
Dependent Claim
38 words
The apparatus according to claim 113 wherein the uncorrectable error indicating circuitry provides the uncorrectable-error signal when the syndrome contains an even number of ones and when the syndrome contains an odd number of ones greater than three.
Claim 125
Dependent Claim
27 words
The apparatus according to claim 114 wherein the uncorrectable error indicating circuitry provides the uncorrectable-error signal when the syndrome contains exactly five ones and exactly seven ones.
Claim 126
Dependent Claim
27 words
The apparatus according to claim 113 wherein the one-bit-error indicating circuitry provides the one-bit-error signal when the syndrome contains an odd number of ones less than five.
Claim 127
Dependent Claim
26 words
The apparatus according to claim 116 wherein the one-bit-error indicating circuitry provides the one-bit-error signal when the syndrome contains exactly one one and exactly three ones.
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USPTO Annuity & Maintenance Windows
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