Dual photo-resist process for fabricating high density DRAM

Claim 2

A process for fabricating a DRAM cell capacitor comprising the steps of: forming a capacitor plate layer on a semiconductor surface; using a first mask, forming a first photo-resist layer on the capacitor plate layer; patterning the first photo-resist layer to define a plurality of first photo-resist regions on said capacitor plate layer, the photo-resist regions being separated from each other by spaces which expose the capacitor layer; after patterning the first photo-resist layer, forming a second photo-resist layer on the capacitor plate layer; shifting the mask in a direction parallel to a surface of the capacitor plate layer and toward a center of the spaces; using the shifted mask, patterning the second photo-resist layer to define a plurality of second photo-resist regions which partially fill said spaces; and etching said capacitor plate layer at said spaces to form a capacitor plate region.

Claim 3

The process of claim 1 further comprising the steps of: after the step of etching depositing a dielectric layer on said etched capacitor plate layer and side walls of said capacitor plate region, and forming a second capacitor plate layer on said deposited dielectric layer.

Claim 4

The process of claim 1 wherein said semiconductor surface is an insulating layer covering a DRAM cell MOSFET, said process further comprising before the step of forming the capacitor plate layer, forming a conducting via between a drain of said MOSFET and said surface on which said capacitor plate layer is formed.

Claim 5

The process of claim 1, wherein the steps of patterning include forming the mask using an i-line stepper photo-lithographic process.

Claim 6

The process of claim 1, further comprising after the step of patterning the first photoresist regions, baking the first photoresist region with ultraviolet light.

Claim 7

A process for fabricating a DRAM comprising the steps of: forming a plurality of MOSFETs each having a drain; forming an insulating layer on said MOSFETs; forming a plurality of vias in said insulating layer, each via connecting the drain of one of the plurality of MOSFETs and a surface of said insulating layer; forming a capacitor plate layer on said insulating layer surface, said capacitor plate layer being connected to each of said vias; forming a first photo,resist layer on the capacitor plate layer; using a mask, patterning the first photo-resist layer to define a first plurality of photo-resist regions on said capacitor plate layer which regions are separated from each other by spaces which expose the capacitor plate layer; forming a second photo-resist layer on the capacitor plate layer; shifting the mask in a direction parallel to a surface of the capacitor plate layer and toward a center of the spaces; patterning the second photo-resist layer to define second photo-resist regions which partially fill said spaces; and after the step of patterning the second photo-resist layer, etching said capacitor plate layer exposed by said spaces to form a plurality of individual capacitor plate regions.

Claim 8

A process for fabricating a DRAM comprising the steps of: forming a plurality of MOSFETs each having a drain; forming an insulating layer on said MOSFETs; forming a plurality of vias in said insulating layer, each via connecting the drain of one of the plurality of MOSFETs and a surface of said insulating layer; forming a capacitor plate layer on said insulating layer surface, said capacitor plate layer being connected to each of said vias; forming a first photo,resist layer on the capacitor plate layer; using a mask, patterning the first photo-resist layer to define a first plurality of photo-resist regions on said capacitor plate layer which regions are separated from each other by spaces which expose the capacitor plate layer; forming a second photo-resist layer on the capacitor plate layer; shifting the mask in a direction parallel to a surface of the capacitor plate layer and toward a center of the spaces; patterning the second photo-resist layer to define second photo-resist regions which partially fill said spaces; and after the step of patterning the second photo-resist layer, etching said capacitor plate layer exposed by said spaces to form a plurality of individual capacitor plate regions.

Claim 9

The process of claim 6 wherein before the step of forming the insulation layer, forming isolation regions for isolating said DRAM cells.

Claim 10

The process of claim 6, wherein the steps of patterning include forming the mask using an i-line stepper photolithographic process.