Split-gate process for non-volatile memory

Claim 1

A method of forming a split-gate memory cell on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a conductive gate overlying said substrate but electrically insulated therefrom by a layer of a first dielectric material, said gate comprising a first conductive layer of material thereon, a second layer of dielectric material formed thereon, and a second conductive layer of material deposited thereon, forming first and second sidewall dielectric spacers adjacent to the first edge and the second opposing edge, respectively of said gate, ion implantation into said substrate of a species of an opposite conductivity type, using a large angle implant, and a third conductive layer of material deposited upon said second conductive layer and said first and second sidewall dielectric spacers, said third conductive material being in electrical contact with said second conductive layer.

Claim 2

A method of forming a split-gate memory cell on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a conductive gate overlying said substrate but electrically insulated therefrom by a layer of a first dielectric material, said gate comprising a first conductive layer of material thereon, a second layer of dielectric material formed thereon, and a second conductive layer of material deposited thereon, forming first and second sidewall dielectric spacers adjacent to the first edge and the second opposing edge, respectively of said gate, ion implantation into said substrate of a species of an opposite conductivity type, using a large angle implant, and a third conductive layer of material deposited upon said second conductive layer and said first and second sidewall dielectric spacers, said third conductive material being in electrical contact with said second conductive layer.

Claim 17

A method of forming a split-gate memory cell on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a gate oxide layer on said substrate, forming a split gate structure having a first edge and a second opposing edge, said split gate structure being formed by the steps: a) forming a first conductive gate overlying said gate oxide layer, said conductive gate comprising material, said first conductive layer comprising a heavily doped layer of polysilicon having a thickness of between about 500 Å and about 2000 Å, formed by thermal decomposition of silane SiH 4 in a reactor at a temperature between about 600° C. and about 650° C. at a pressure of between about 0.2 Torr and about 1.0 Torr using 100% silane or a diluted mixture of between about 20% and about 30% silane in nitrogen, b) forming an interconductor dielectric layer on said first conductive gate which comprises a bottom layer of oxide, a middle layer of nitride and a top layer of oxide, wherein said bottom layer of oxide is deposited by thermal oxidation or CVD to a thickness of between about 50 Å and about 100 Å, said nitride is deposited by a LPCVD silicon nitride deposition process to a thickness of between about 80 Å and about 180 Å and said top layer of oxide is deposited by thermal oxidation or CVD to a thickness of between about 30 Å and about 80 Å, c) forming a second conductive layer of material on said layer of dielectric material said second conductive layer comprising polysilicon having a thickness of between about 200 Å and about 2000 Å, forming the second conductive layer of said split-gate, said second conductive layer comprising a heavily doped layer of polysilicon formed by LPCVD deposition of polysilicon, forming first and second sidewall dielectric spacers adjacent to the first edge and the second opposing edge, respectively of said gate, by CVD deposition of SiO 2 to a thickness of between about 1000 Å and about 3000 Å followed by etching of said CVD SiO 2 to form said dielectric spacers, ion implanting into said substrate of a species of an opposite conductivity type, using a large angle implant of N+ dopant ions being applied using the process of Large-Angle-Implant to produce off-set Source/Drain regions in said substrate of said split-gate device, with a dopant comprising arsenic (As) with a dose of between about 1 and 8×10 15 cm -2 , implanted at an energy of between about 50 keV and about 100 keV in a high current LAI implanter, and forming a third conductive layer of material selected from the group consisting of polysilicon and polycide upon said second conductive layer and said first and second sidewall dielectric spacers, said third conductive material being in electrical contact with said second conductive layer.

Claim 18

A method of forming a split-gate memory cell on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a gate oxide layer on said substrate, forming a split gate structure having a first edge and a second opposing edge, said split gate structure being formed by the steps: a) forming a first conductive gate overlying said gate oxide layer, said conductive gate comprising material, said first conductive layer comprising a heavily doped layer of polysilicon having a thickness of between about 500 Å and about 2000 Å, formed by thermal decomposition of silane SiH 4 in a reactor at a temperature between about 600° C. and about 650° C. at a pressure of between about 0.2 Torr and about 1.0 Torr using 100% silane or a diluted mixture of between about 20% and about 30% silane in nitrogen, b) forming an interconductor dielectric layer on said first conductive gate which comprises a bottom layer of oxide, a middle layer of nitride and a top layer of oxide, wherein said bottom layer of oxide is deposited by thermal oxidation or CVD to a thickness of between about 50 Å and about 100 Å, said nitride is deposited by a LPCVD silicon nitride deposition process to a thickness of between about 80 Å and about 180 Å and said top layer of oxide is deposited by thermal oxidation or CVD to a thickness of between about 30 Å and about 80 Å, c) forming a second conductive layer of material on said layer of dielectric material said second conductive layer comprising polysilicon having a thickness of between about 200 Å and about 2000 Å, forming the second conductive layer of said split-gate, said second conductive layer comprising a heavily doped layer of polysilicon formed by LPCVD deposition of polysilicon, forming first and second sidewall dielectric spacers adjacent to the first edge and the second opposing edge, respectively of said gate, by CVD deposition of SiO 2 to a thickness of between about 1000 Å and about 3000 Å followed by etching of said CVD SiO 2 to form said dielectric spacers, ion implanting into said substrate of a species of an opposite conductivity type, using a large angle implant of N+ dopant ions being applied using the process of Large-Angle-Implant to produce off-set Source/Drain regions in said substrate of said split-gate device, with a dopant comprising arsenic (As) with a dose of between about 1 and 8×10 15 cm -2 , implanted at an energy of between about 50 keV and about 100 keV in a high current LAI implanter, and forming a third conductive layer of material selected from the group consisting of polysilicon and polycide upon said second conductive layer and said first and second sidewall dielectric spacers, said third conductive material being in electrical contact with said second conductive layer.