US5499209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage
Assignee: Toshiba Corp
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Filing: 1995-06-01
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Granted: 1996-03-12
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Expires: 2015-06-01
Abstract
Abstract A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.
Inventors
- 👤 Yukihito Oowaki
- 👤 Daisaburo Takashima
- 👤 Masako Ohta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A random-access memory comprising: an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor; bit lines associated with said memory cells at current carrying electrodes of said transistors; word lines associated with said memory cells at control gates of said transistors; and a driver circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, said driver circuit including at least one capacitor having a first insulated electrode and a second insulated electrode, and a circuit for supplying a regulated voltage, which is substantially independent of variation in the power supply voltage, to at least one of said first insulated electrode and second insulated electrode.
Claim 2
Dependent Claim
165 words
A random-access memory comprising: an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor; bit lines associated with said memory cells at current carrying electrodes of said transistors; word lines associated with said memory cells at control gates of said transistors; and a driver circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, said driver circuit including at least one capacitor having a first insulated electrode and a second insulated electrode, and a circuit for supplying a regulated voltage, which is substantially independent of variation in the power supply voltage, to at least one of said first insulated electrode and second insulated electrode.
Claim 3
Dependent Claim
199 words
A random access memory comprising: an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor; bit lines associated with said memory cells at current carrying electrodes of said transistor; word lines associated with said memory cells at control gates of said transistors; and a drive circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, wherein said driver circuit comprises: a charge-up capacitor having a first and a second insulated electrodes; a first circuit connected to the first electrode, for supplying it with a first regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential; and a second circuit connected to the second electrode, for supplying it with a second regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential.
Claim 4
Dependent Claim
199 words
A random access memory comprising: an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor; bit lines associated with said memory cells at current carrying electrodes of said transistor; word lines associated with said memory cells at control gates of said transistors; and a drive circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, wherein said driver circuit comprises: a charge-up capacitor having a first and a second insulated electrodes; a first circuit connected to the first electrode, for supplying it with a first regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential; and a second circuit connected to the second electrode, for supplying it with a second regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential.
Claim 5
Dependent Claim
44 words
A memory according to claim 2, wherein said first circuit comprises: at least one diode-connected metal-insulator-semiconductor field effect transistor connected at its one current carrying electrode to the power supply voltage; and an amplifier connected to the current carrying electrode of said field-effect transistor.
Claim 6
Dependent Claim
45 words
A memory according to claim 2, wherein said second circuit comprises: at least one diode-connected metal-insulator-semiconductor field effect transistor connected at its one current carrying electrode to the power supply voltage; and an amplifier connected to the current carrying electrode of said field effect transistor.
Claim 7
Dependent Claim
49 words
A memory according to claim 2, wherein each of the first and second circuits comprises: at least one diode-connected metal-insulator-semiconductor field effect transistor connected at its one current carrying electrode to the power supply voltage; and an amplifier connected to the current carrying electrode of said field effect transistor.
Claim 8
Dependent Claim
57 words
A memory according to claim 2, wherein at least one of the first and second circuits comprises: a series circuit of diode-connected metal-insulator-semiconductor field effect transistors connected at its one end to the power supply voltage and the other end thereof to a ground potential; and an amplifier connected to said one end of the series circuit.
Claim 9
Dependent Claim
92 words
A memory according to claim 2, wherein at least one of the first and second circuits comprises: dielectric breakdown compensator means for generating a constant d.c. voltage while the power supply voltage is less than a predetermined potential level, and for generating while the power supply voltage is greater than the predetermined potential level a linearly-variable voltage that is substantially proportional to variation in dielectric breakdown voltage in the data transfer transistor of the selected memory cell so as to compensate for deviation in the dielectric breakdown voltages among said memory cells.
Claim 10
Dependent Claim
42 words
A memory according to claim 2, further comprising: an additional circuit means for detecting a current leakage component inherent in the selected word line, and for selectively providing said word line with a voltage that compensates for a detected current leakage component.
Claim 11
Dependent Claim
73 words
A memory according to claim 8, wherein said additional circuit means comprises: a comparator circuit including a differential amplifier with a first input for receiving the actual voltage on said selected word line and a second input for receiving a reference signal representing a desired potential level on said word line; a ring-oscillator circuit for oscillating in response to an output of said comparator; and a charge-pump circuit connected to said oscillator circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |