Semiconductor memory device selectively operating divided memory blocks

Claim 2

A semiconductor memory device, comprising: a plurality of memory blocks having a plurality of common row addresses and being operated selectively, said plurality of memory blocks each including a plurality of memory cell arrays, a plurality of bit line pairs provided corresponding to said plurality of memory cell arrays and corresponding to said plurality of common row addresses, a plurality of switching means provided corresponding to said plurality of bit line pairs, and an input/output data line pair connected to said plurality of bit line pairs through said plurality of switching means; first row selecting means for generating a row select signal selecting a common row address; and second row selecting means receiving a memory block select signal indicating selected said memory block and said row select signal, and responsive to these signals for turning on said switching means corresponding to the selected row address in the selected memory block.

Claim 3

The semiconductor memory device as recited in claim 1, wherein said plurality of bit line pairs are initially charged to a first potential when a corresponding memory block is in a non-selected state, and said input/output data line pair is initially charged to a second potential higher than said first potential when a corresponding memory block is in a non-selected state.

Claim 4

The semiconductor memory device as recited in claim 1, wherein said plurality of memory blocks each further include first equalize means provided corresponding to said plurality of bit line pairs for equalizing corresponding said bit line pair to a first potential when corresponding said memory block is in a non-selected state, and second equalize means for equalizing corresponding said input/output data line pair to a second potential higher than said first potential.

Claim 5

The semiconductor memory device as recited in claim 3, wherein said plurality of memory blocks each further include sense amplifier means provided corresponding to said plurality of bit line pairs for sensing and amplifying a potential difference of corresponding said bit line pair when corresponding said memory block is in a selected state.

Claim 6

The semiconductor memory device as recited in claim 4, wherein said plurality of memory cell arrays each include a plurality of dynamic type memory cells.

Claim 7

A semiconductor memory device, comprising: a plurality of memory blocks having a plurality of common row addresses and being operated selectively, said plurality of memory blocks each including a plurality of memory cell arrays, a plurality of bit line pairs provided corresponding to said plurality of memory cell arrays and corresponding to said plurality of common row addresses, a plurality of switching means provided corresponding to said plurality of bit line pairs, and an input/output data line pair connected to said plurality of bit line pairs through said plurality of switching means; first row selecting means for generating a row select signal for selection one of said common row addresses; and a plurality of second row selecting means provided corresponding to said plurality of common row addresses and each receiving a memory block select signal indicating a selected memory block and corresponding said row select signal, for turning on said switching means corresponding to the selected common row address in the selected memory block in response to these signals.

Claim 8

A semiconductor memory device, comprising: a plurality of memory blocks having a plurality of common row addresses and being operated selectively, said plurality of memory blocks each including a plurality of memory cell arrays, a plurality of bit line pairs provided corresponding to said plurality of memory cell arrays and corresponding to said plurality of common row addresses, a plurality of switching means provided corresponding to said plurality of bit line pairs, and an input/output data line pair connected to said plurality of bit line pairs through said plurality of switching means; first row selecting means for generating a row select signal for selection one of said common row addresses; and a plurality of second row selecting means provided corresponding to said plurality of common row addresses and each receiving a memory block select signal indicating a selected memory block and corresponding said row select signal, for turning on said switching means corresponding to the selected common row address in the selected memory block in response to these signals.

Claim 9

The semiconductor memory device as recited in claim 6, wherein said plurality of bit line pairs are initially charged to a first potential when a corresponding memory block is in a non-selected state, and said input/output data line pair is initially charged to a second potential higher than said first potential when the corresponding memory block is in a non-selected state.

Claim 10

The semiconductor memory device as recited in claim 6, wherein said memory block select signal is formed of a plurality of block select signals corresponding to said plurality of memory blocks, a signal corresponding to a selected memory block among the block select signals being activated, each of said row select signals is activated when a corresponding row address is selected, and said plurality of second row selecting means each include a plurality of logic means provided corresponding to said plurality of memory blocks for each providing a logic signal turning on said switching means of corresponding said memory block when corresponding said block select signal and corresponding said row select signal are both activated.

Claim 11

The semiconductor memory device as recited in claim 8, wherein said plurality of memory blocks each include first equalize means provided corresponding to said plurality of bit line pairs for equalizing corresponding said bit line pair to a first potential when corresponding said memory block is in a non-selected state, and second equalize means for equalizing corresponding said input/output data line pair to a second potential higher than said first potential.

Claim 12

The semiconductor memory device as recited in claim 9, wherein said plurality of memory blocks each further include sense amplifier means provided corresponding to said plurality of bit line pairs for sensing and amplifying a potential difference of corresponding said bit line pair when corresponding said memory block is in a selected state.

Claim 13

The semiconductor memory device as recited in claim 10, wherein said plurality of memory cell arrays each include a plurality of dynamic type memory cells.