US5500805A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple source equalization design utilizing metal interconnects for gate arrays and embedded arrays
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-09-02
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Granted: 1996-03-19
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Expires: 2014-09-02
Abstract
Abstract In accordance with the teachings of this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.
Inventors
- 👤 Ven L. Lee
- 👤 William M. Dawson
- 👤 Donald L. Doud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
195 words
A method for fabricating a plurality of integrated circuits from a plurality of alternate sources, each of said plurality of integrated circuits performing substantially identically regardless of inherent process differences of said plurality of alternate sources, comprising the steps of: designing a circuit to perform a desired electrical function; determining a first characteristic capacitance for a given electrical interconnect routing for an integrated circuit produced by a first alternate source using a first fabrication process; determining a second characteristic capacitance for a similar electrical interconnect routing for an integrated circuit produced by a second alternate source using a second fabrication process; determining a difference in said first and second characteristic capacitances; laying out said circuit to provide a first layout for fabrication by a first alternate source using said first fabrication process; and adjusting said first layout to adapt for said difference in said first and second characteristic capacitances to provide a second layout for fabrication by said second alternate source using said second fabrication process, by adjusting said first layout to provide said second layout by adjusting electrical interconnect widths to alter the capacitance associated therewith to compensate for said difference in characteristic capacitances.
Claim 2
Independent Claim
195 words
A method for fabricating a plurality of integrated circuits from a plurality of alternate sources, each of said plurality of integrated circuits performing substantially identically regardless of inherent process differences of said plurality of alternate sources, comprising the steps of: designing a circuit to perform a desired electrical function; determining a first characteristic capacitance for a given electrical interconnect routing for an integrated circuit produced by a first alternate source using a first fabrication process; determining a second characteristic capacitance for a similar electrical interconnect routing for an integrated circuit produced by a second alternate source using a second fabrication process; determining a difference in said first and second characteristic capacitances; laying out said circuit to provide a first layout for fabrication by a first alternate source using said first fabrication process; and adjusting said first layout to adapt for said difference in said first and second characteristic capacitances to provide a second layout for fabrication by said second alternate source using said second fabrication process, by adjusting said first layout to provide said second layout by adjusting electrical interconnect widths to alter the capacitance associated therewith to compensate for said difference in characteristic capacitances.
Claim 3
Dependent Claim
41 words
A method as in claim 1 wherein said step of adjusting said first layout to provide said second layout comprises the step of adjusting electrical interconnect widths to alter the capacitance associated therewith to compensate for said difference in characteristic capacitances.
Claim 4
Dependent Claim
25 words
A method as in claim 1 wherein said step of adjusting maintains the length of metal interconnects, as measured by the number of grid spacings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |