US5506804A
Expired / Lapsed
US
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Dynamic Random Access Type Semiconductor Device
Assignee: Micron Memory Japan Ltd
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Filing: 1993-11-30
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Granted: 1996-04-09
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Expires: 2013-11-30
Abstract
Abstract A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
Inventors
- 👤 Kazumasa Yanagisawa
- 👤 Tatsuyuki Ohta
- 👤 Tetsu Udagawa
- 👤 Kyoko Ishii
- 👤 Hitoshi Miwa
- 👤 Atsushi Nozoe
- 👤 Masayuki Nakamura
- 👤 Tetsurou Matsumoto
- 👤 Yoshitaka Kinoshita
- 👤 Yoshiaki Ouchi
- 👤 Hiromi Tsukada
- 👤 Shoji Wada
- 👤 Kazuo Mihashi
- 👤 Yutaka Kobayashi
- 👤 Goro Kitsukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/28; G11C29/30; G11C29/34; G11C29/46; G11C29/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
240 words
A semiconductor memory device comprising: a plurality of word lines and a plurality of data lines; a plurality of dynamic memory cells each of which is coupled to a corresponding one of said plurality of word lines and a corresponding one of said plurality of data lines; an oscillator outputting pulse signals having a predetermined frequency; a voltage forming circuit receiving a supply voltage having a magnitude based on a reference potential and forming a boosted voltage on the basis of said pulse signals, said boosted voltage having an absolute value larger than that of said supply voltage as compared to the reference potential; a switch circuit coupled between said oscillator and said voltage forming circuit, a control circuit receiving said boosted voltage and controlling said switch circuit so that said switch circuit transmits said pulse signals from said oscillator to said voltage forming circuit in the case where the absolute value of said boosted voltage is smaller than that of a predetermined voltage and does not transmit said pulse signals from said oscillator to said voltage forming circuit in the case where the absolute value of said boosted voltage is larger than or equal to that of said predetermined voltage; and a word line drive circuit receiving a plurality of selection signals and said boosted voltage and supplying said boosted voltage to at least one of said plurality of word lines in accordance with said plurality of selection signals.
Claim 2
Dependent Claim
240 words
A semiconductor memory device comprising: a plurality of word lines and a plurality of data lines; a plurality of dynamic memory cells each of which is coupled to a corresponding one of said plurality of word lines and a corresponding one of said plurality of data lines; an oscillator outputting pulse signals having a predetermined frequency; a voltage forming circuit receiving a supply voltage having a magnitude based on a reference potential and forming a boosted voltage on the basis of said pulse signals, said boosted voltage having an absolute value larger than that of said supply voltage as compared to the reference potential; a switch circuit coupled between said oscillator and said voltage forming circuit, a control circuit receiving said boosted voltage and controlling said switch circuit so that said switch circuit transmits said pulse signals from said oscillator to said voltage forming circuit in the case where the absolute value of said boosted voltage is smaller than that of a predetermined voltage and does not transmit said pulse signals from said oscillator to said voltage forming circuit in the case where the absolute value of said boosted voltage is larger than or equal to that of said predetermined voltage; and a word line drive circuit receiving a plurality of selection signals and said boosted voltage and supplying said boosted voltage to at least one of said plurality of word lines in accordance with said plurality of selection signals.
Claim 3
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said reference potential is ground potential.
Claim 4
Dependent Claim
87 words
A semiconductor memory device according to claim 2, wherein said word line drive circuit comprises a P-channel MOSFET having a gate, a source coupled to receive said boosted voltage and a drain coupled to a corresponding one of said plurality of word lines and an N-channel MOSFET having a gate coupled to said gate of said P-channel MOSFET, a drain coupled to said drain of said P-channel MOSFET and a source coupled to receive said ground potential, and wherein said voltage forming circuit comprises voltage boosting capacitors.
Claim 5
Dependent Claim
110 words
A semiconductor memory device according to claim 3, wherein said control circuit outputs a control signal, said control signal being a high level in the case in which the absolute value of said boosted voltage is smaller than that of said predetermined voltage and being a low level in the case in which the absolute value of said boosted voltage is larger than or equal to that of said predetermined voltage, and wherein said switch circuit comprises a NAND circuit having a first input terminal coupled to receive said pulse signals, a second input terminal coupled to receive said control signal and an output terminal for outputting said pulse signals.
Claim 6
Dependent Claim
27 words
A semiconductor memory device according to claim 4, wherein each of said plurality of dynamic memory cells comprises an information storing capacitor and an address selecting MOSFET.
Claim 7
Dependent Claim
56 words
A semiconductor memory device according to claim 1, further comprising: a voltage generator receiving said supply voltage and forming a substrate back bias voltage on the basis of said pulse signals outputted from said oscillator, said substrate back bias voltage having the polarity opposite to that of said supply voltage as compared to said reference potential.
Claim 8
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein said reference potential is ground potential.
Claim 9
Dependent Claim
77 words
A semiconductor memory device according to claim 7, wherein said word line drive circuit comprises a P-channel MOSFET having a gate, a source coupled to receive said boosted voltage and a drain coupled to a corresponding one of said plurality of word lines and an N-channel MOSFET having a gate coupled to said gate of said P-channel MOSFET, a drain coupled to said drain of said P-channel MOSFET and a source coupled to receive said ground potential.
Claim 10
Dependent Claim
27 words
A semiconductor memory device according to claim 8, wherein each of said plurality of dynamic memory cells comprises an information storing capacitor and an address selecting MOSFET.
References Cited (Backward Citations)
JPS58188388A
Cited
JPS61170992A
Cited
JPS6221323A
Cited
US4777625A
Cited
US4961170A
Cited
US5150325A
Cited
US5077691A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |