Timing recovery apparatus

Claim 1

A timing recovery apparatus comprising: first and second reference signal sources; first and second dividing means for scaling the respective first and second reference signals; a first counter means connected to an output of the second dividing means; a storing means having a first input connected to an output from the first counter means; a second counter means connected to an output of the first dividing means and having an output connected to a second input of the storing means; a calculation means for calculating a value equal to a complete number of source network clock cycles divided by a predetermined integer value which is loaded into the second counter means when a cell sequence count reaches a first predetermined value, and when the second counter means reaches a second predetermined value the contents of the storing means represents a new residual time stamp value, wherein the value calculated by the calculation means is ##EQU2## and y r =RTS r -RTS r-1 -{M nom }modulo 2 p ±n·2 p , n integer such that -2 p-1 <y r <2 p-1 where: M 1 is the value calculated by the calculation means; M 1r is the value of M 1 after the rth iteration of the calculation; N is the number of bits of user data carried in 8 successive ATM cells; f n X 1 is a source network clock frequency of said source divided by a predefined value; M nom is the number of complete clock pulses at the frequency fn 1 x 1 in the time it takes to generate N clock pulses at the source clock rate; y r is the difference between M nom and the actual number of network clock pulses as indicated by the Residual Time Stamp values; f s is the frequency of the source clock; RTS is the RTS value derived from the incoming ATM cell stream in accordance with CCITT Draft Recommendation I.363; RTS r is the rth value of the RTS value; P is the length (in bits) of the first counter means.