US5506953A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory mapped video control registers
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-12-22
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Granted: 1996-04-09
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Expires: 2014-12-22
Abstract
Abstract A video controller uses memory-mapping to address registers in the video controller to enhance speed of the computer system. The memory-map registers may be mapped to a high address area located within the address space of the frame buffer or to a low address area below one megabyte.
Inventors
- 👤 Giang H. Dao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:20
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063; G09G5/39; G09G2360/00; G09G2360/12; G09G2360/125
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
123 words
A video controller comprising: a video memory; a first set of registers for storing control information; a second set of registers for defining: a first address space for said video memory in high memory; a second address space for addressing said first set of registers in low memory addresses using memory mapped addresses; whether memory mapping is used to address said first set of registers; and whether memory mapping, if used, directs addresses to low memory or high memory; and decode logic coupled to said first set of registers and said second set of registers, comprising: circuitry to identify memory mapped addresses directed to said first set of registers; and circuitry to identify I/O mapped addresses directed to said first set of registers.
Claim 2
Dependent Claim
123 words
A video controller comprising: a video memory; a first set of registers for storing control information; a second set of registers for defining: a first address space for said video memory in high memory; a second address space for addressing said first set of registers in low memory addresses using memory mapped addresses; whether memory mapping is used to address said first set of registers; and whether memory mapping, if used, directs addresses to low memory or high memory; and decode logic coupled to said first set of registers and said second set of registers, comprising: circuitry to identify memory mapped addresses directed to said first set of registers; and circuitry to identify I/O mapped addresses directed to said first set of registers.
Claim 3
Dependent Claim
30 words
The video controller of claim 1 wherein said circuitry to identify memory mapped addresses includes circuitry to identify memory mapped addresses within a predetermined portion of said first address space.
Claim 4
Dependent Claim
42 words
The video controller of claim 2 wherein said circuitry to identify memory mapped addresses further includes circuitry for identifying one of said first set of registers in response to a memory mapped address within said predetermined portion of said first address space.
Claim 5
Independent Claim
124 words
A method of storing display information in a video controller comprising the steps of: transferring data to a video memory responsive to control information in a first set of registers; defining in a second set of registers: a first address space for said video memory in high memory; a second address space for addressing said first set of registers in low memory addresses using memory mapped addresses; whether memory mapping is used to address said first set .Of registers; and whether memory mapping, if used, directs addresses to low memory or high memory; and responsive to said second set of registers: identifying memory mapped addresses directed to said first set of registers and identifying I/O mapped addresses directed to said first set of registers.
Claim 6
Independent Claim
124 words
A method of storing display information in a video controller comprising the steps of: transferring data to a video memory responsive to control information in a first set of registers; defining in a second set of registers: a first address space for said video memory in high memory; a second address space for addressing said first set of registers in low memory addresses using memory mapped addresses; whether memory mapping is used to address said first set .Of registers; and whether memory mapping, if used, directs addresses to low memory or high memory; and responsive to said second set of registers: identifying memory mapped addresses directed to said first set of registers and identifying I/O mapped addresses directed to said first set of registers.
Claim 7
Dependent Claim
30 words
The method of claim 4 wherein said step of identifying memory mapped addresses includes the step of identifying memory mapped addresses within a predetermined portion of said first address space.
Claim 8
Dependent Claim
42 words
The method of claim 5 wherein said step of identifying memory mapped addresses further includes the step of identifying one of said first set of registers in response to a memory mapped address within said predetermined portion of said first address space.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |