US5511033A
Expired / Lapsed
US
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Hidden self-refresh method and apparatus for synchronous dynamic random access memory
Assignee: SK Hynix Inc
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Filing: 1994-11-08
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Granted: 1996-04-23
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Expires: 2014-11-08
Abstract
Abstract Hidden self-refresh method and apparatus for a synchronous dynamic random access memory having at least two cell banks, each of the cell banks including a plurality of cell arrays. The hidden self-refresh apparatus comprises a first input line for inputting an external first address signal for addressing any one of the cell banks, a second input line for inputting an external second address signal for addressing any one of the cell arrays in the cell banks, a counter for generating a refresh address signal for addressing any one of the plurality of cell arrays in one of the cell banks corresponding to a logical value of the first address signal from the first input line, an address multiplexer for selecting either the refresh address signal from the counter or the second address signal from the second input line, and at least two latch circuits being individually driven according to the logical value of the first address signal from the first input line, each of the at least two latch circuits transferring the address signal selected by the address multiplexer to a corresponding one of the cell banks.
Inventors
- 👤 Chang H. Jung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40615; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
158 words
A method of controlling a hidden self-refresh operation of a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, comprising the steps of: inputting an external first address signal for addressing any one of said cell banks; generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to a logical value of said first address signal; inputting an external second address signal for addressing any one of said cell arrays in said cell banks; selecting successively said second address signal and said refresh address signal; and latching said successively selected address signals dispersedly to said cell banks according to the logical value of said first address signal in such a manner that respective applications of said second address signal and said refresh address signal to said cell banks coincide partially with each other.
Claim 2
Independent Claim
158 words
A method of controlling a hidden self-refresh operation of a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, comprising the steps of: inputting an external first address signal for addressing any one of said cell banks; generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to a logical value of said first address signal; inputting an external second address signal for addressing any one of said cell arrays in said cell banks; selecting successively said second address signal and said refresh address signal; and latching said successively selected address signals dispersedly to said cell banks according to the logical value of said first address signal in such a manner that respective applications of said second address signal and said refresh address signal to said cell banks coincide partially with each other.
Claim 3
Dependent Claim
183 words
In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising: first input means for inputting an external first address signal for addressing any one of said cell banks; second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks; counting means for generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to a logical value of said first address signal from said first input means; multiplexing means for selecting either said refresh address signal from said counting means or said second address signal from said second input means; and at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh or second address signals selected by said multiplexing means to a corresponding one of said cell banks.
Claim 4
Dependent Claim
183 words
In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising: first input means for inputting an external first address signal for addressing any one of said cell banks; second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks; counting means for generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to a logical value of said first address signal from said first input means; multiplexing means for selecting either said refresh address signal from said counting means or said second address signal from said second input means; and at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh or second address signals selected by said multiplexing means to a corresponding one of said cell banks.
Claim 5
Dependent Claim
174 words
A hidden self-refresh apparatus as set forth in claim 2, wherein said counting means includes: at least two registers, each of said at least two registers storing an address of the finally refreshed cell array in a corresponding one of said cell banks; addition means for adding 1 to said refresh address signal from any one of said at least two registers and outputting the resultant refresh address signal to said multiplexing means; at least two switching devices being individually driven according to the logical value of said first address signal from said first input means, each of said at least two switching devices transferring said refresh address signal from said addition means to a corresponding one of said at least two registers; and at least two switching devices being individually driven according to the logical value of said first address signal from said first input means, each of said at least two switching devices transferring said refresh address signal from a corresponding one of said at least two registers to said addition means.
Claim 6
Dependent Claim
214 words
In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising: first input means for inputting an external first address signal for addressing said cell banks; second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks; at least two counting means being individually driven according to a logical value of said first address signal from said first input means, each of said at least two counting means generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to the logical value of said first address signal from said first input means; multiplexing means for selecting either said refresh address signal from any one of said at least two counting means or said second address signal from said second input means; and at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh and second address signals selected by said multiplexing means to a corresponding one of said cell banks.
Claim 7
Dependent Claim
214 words
In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising: first input means for inputting an external first address signal for addressing said cell banks; second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks; at least two counting means being individually driven according to a logical value of said first address signal from said first input means, each of said at least two counting means generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to the logical value of said first address signal from said first input means; multiplexing means for selecting either said refresh address signal from any one of said at least two counting means or said second address signal from said second input means; and at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh and second address signals selected by said multiplexing means to a corresponding one of said cell banks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |