Huffman encoding method, circuit and system employing most significant bit change for size detection

Claim 3

The method of Huffman encoding of claim 1, wherein: said step of detecting a bit position of a greatest significant bit that differs from a most significant bit of a next multibit signed digital number includes forming an absolute value of said next multibit signed digital number of the series, detecting a bit position of a greatest significant "1" bit of said absolute value of said next multibit signed digital number.

Claim 4

The method of Huffman encoding of claim 2, wherein: said step of forming said absolute value of said next multibit signed digital number includes determining if said next multibit signed digital number is greater than or equal to zero, subtracting said next multibit signed digital number from zero if said next multibit signed digital number is not greater than or equal to zero, and returning said next multibit signed digital number if said next multibit signed digital number is greater than or equal to zero.

Claim 5

The method of Huffman encoding of claim 2, wherein: said step of generating a data size digital number includes forming a size digital number having a value corresponding to said detected position of the greatest significant "1" bit of said absolute value of said next multibit signed digital number.

Claim 6

The method of Huffman encoding of claim 4, wherein: said step of selecting from said next multibit signed digital number a number of least significant bits corresponding to said data size digital number includes forming a multibit digital mask having a number of least significant "1's" equal to said size digital number and a number of most significant "0's" whereby said multibit digital mask has the same number of bits as said next multibit signed digital number, and forming a bit wise AND of said next multibit signed digital number and said multibit digital mask.

Claim 7

The method of Huffman encoding of claim 1, wherein: said step of selecting from said next multibit signed digital number a number of least significant bits corresponding to the data size digital number includes forming a multibit digital mask having a number of least significant "1's" equal to said value of said data size digital number and a number of most significant "0's" whereby the multibit digital mask has the same number of bits as said next multibit signed digital number, and forming the bit wise AND of said next multibit signed digital number and the multibit digital mask.

Claim 8

A data processing apparatus for Huffman encoding a series of multibit signed digital numbers comprising: a set of a plurality of data registers, said number stored in a first data register; a left most bit change detector having an input connected to said set of data registers and an output, said left most bit change detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which differs from a most significant bit of the signal at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply data stored in said first data register to said input of said left most bit change detector, store said output of said left most bit change detector in a second data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said second data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 9

A data processing apparatus for Huffman encoding a series of multibit signed digital numbers comprising: a set of a plurality of data registers, said number stored in a first data register; a left most bit change detector having an input connected to said set of data registers and an output, said left most bit change detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which differs from a most significant bit of the signal at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply data stored in said first data register to said input of said left most bit change detector, store said output of said left most bit change detector in a second data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said second data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 10

The data processing apparatus of claim 7, further comprising: a barrel rotator having an input connected to said set of data registers, a rotate control input and an output, said barrel rotator generating at said output a multibit digital signal corresponding to a signal at said input rotated an amount corresponding to a signal at said rotate control input; and wherein said instruction decoder is further responsive to a fourth instruction to supply data stored in said second data register to said input of said barrel rotator, supply data stored in said second data register to said rotate control input of said barrel rotator, and store said output of said barrel rotator in a third data register, and wherein said instruction decoder is further responsive to a fifth instruction to supply data stored in said third data register to said first input of said arithmetic logic unit, supply data stored in said first data register to said second input of said arithmetic logic unit, supply data stored in said second data register to said third input of said arithmetic logic unit, control said arithmetic logic unit to output bits supplied to said first input if corresponding bits of said third input have a first digital state and to output bit supplied to said second input is corresponding bits of said third input have a second digital state opposite to said first digital state, and store said output of said arithmetic logic unit in a fifth data register.

Claim 11

An data processing system for Huffman encoding a series of multibit signed digital numbers comprising: an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a set of a plurality of data registers, said number stored in a first data register; a left most bit change detector having an input connected to said set of data registers and an output, said left most bit change detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which differs from a most significant bit of the signal at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply data stored in said first data register to said input of said left most bit change detector, store said output of said left most bit change detector in a second data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said second data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 12

An data processing system for Huffman encoding a series of multibit signed digital numbers comprising: an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a set of a plurality of data registers, said number stored in a first data register; a left most bit change detector having an input connected to said set of data registers and an output, said left most bit change detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which differs from a most significant bit of the signal at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply data stored in said first data register to said input of said left most bit change detector, store said output of said left most bit change detector in a second data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said second data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 13

The data processing system of claim 9, wherein: said data processor circuit further includes a barrel rotator having an input connected to said set of data registers, a rotate control input and an output, said barrel rotator generating at said output a multibit digital signal corresponding to a signal at said input rotated an amount corresponding to a signal at said rotate control input; and wherein said instruction decoder is further responsive to a fourth instruction to supply data stored in said second data register to said input of said barrel rotator, supply data stored in said second data register to said rotate control input of said barrel rotator, store said output of said barrel rotator in a third data register, and wherein said instruction decoder is further responsive to a fifth instruction to supply data stored in said third data register to said first input of said arithmetic logic unit, supply data stored in said first data register to said second input of said arithmetic logic unit, supply data stored in said second data register to said third input of said arithmetic logic unit, control said arithmetic logic unit to output bits supplied to said first input if corresponding bits of said third input have a first digital state and to output bit supplied to said second input is corresponding bits of said third input have a second digital state opposite to said first digital state, and store said output of said arithmetic logic unit in a fifth data register.

Claim 14

The data processing system of claim 9, wherein: said data processor circuit further includes a plurality of data memories connected to said data processor circuit, an instruction memory supplying instructions to said data processor circuit, and a transfer controller connected to said data system bus, each of said data memories and said instruction memory controlling data transfer between said system memory and said plurality of data memories and between said system memory and said instruction memory.

Claim 15

The data processing system of claim 11, wherein: said data processor circuit further includes at least one additional data processor circuit identical to said data processor circuit, a plurality of additional data memories connected to each additional data processor circuit, an additional instruction memory supplying instructions to each additional data processor circuit, and said transfer controller is further connected to each of said additional data memories and each said additional instruction memory controlling data transfer between said system memory and said each of said additional data memories and between said system memory and each said additional instruction memory.

Claim 16

The data processing system of claim 12, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, each of said additional data processor circuits, each of said additional data memories, each additional instruction memory and said transfer controller are formed on a single integrated circuit.

Claim 17

The data processing system of claim 11, wherein: said data processor circuit further includes a master data processor, a plurality of master data memories connected to said master data processor, at least one master instruction memory supplying instructions to said master data processor, and said transfer controller is further connected to each of said master data memories and each said master instruction memory controlling data transfer between said system memory and said each of said master data memories and between said system memory and each said master instruction memory.

Claim 18

The data processing system of claim 14, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, said master data processor, each of said master data memories, each master instruction memory and said transfer controller are formed on a single integrated circuit.

Claim 19

The data processor system of claim 9, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an image display unit connected to said image memory generating a visually perceivable output of an image consisting of a plurality of pixels stored in said image memory.

Claim 20

The data processor system of claim 16, further comprising: a palette forming a connection between said image memory and said image display unit, said palette transforming pixels recalled from said image memory into video signals driving said image display unit; and wherein said data processor circuit further includes a frame controller connected to said palette controlling said palette transformation of pixels into video signals.

Claim 21

The data processor system of claim 9, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: a printer connected to said image memory generating a printed output of an image consisting of a plurality of pixels stored in said image memory.

Claim 22

The data processor system of claim 18, wherein: said printer consists of a color printer.

Claim 23

The data processor system of claim 18, further comprising: a printer controller forming a connection between said image memory and said printer, said printer controller transforming pixels recalled from said image memory into print signals driving said printer; and wherein said data processor circuit further includes a frame controller connected to said print controller controlling said print controller transformation of pixels into print signals.

Claim 24

The data processor system of claim 9, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an imaging device connected to said image memory generating an image signal input.

Claim 25

The data processor system of claim 21, further comprising: an image capture controller forming a connection between said imaging device and said image memory, said image capture controller transforming said image signal into pixels supplied for storage in said image memory; and wherein said data processor circuit further includes a frame controller connected to said image capture controller controlling said image capture controller transformation of said image signal into pixels.

Claim 26

The data processor system of claim 9, further comprising: a modem connected to said data system bus and to a communications line.

Claim 27

The data processor system of claim 9, further comprising: a host processing system connected to said data system bus.

Claim 28

The data processor system of claim 24, further comprising: a host system bus connected to said host processing system transferring data and addresses; and at least one host peripheral connected to said host system bus.

Claim 29

A data processing apparatus for Huffman encoding a series of multibit signed digital numbers comprising: a set of a plurality of data registers, said number stored in a first data register; a left most one detector having an input connected to said set of data registers and an output, said left most one detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which has a "1" at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply a multibit digital number equal to zero to said first input of said arithmetic logic unit, supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to subtract said second input from said first input, store said output of said arithmetic logic unit in a second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero, store data stored in said first data register in said second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was greater than or equal to zero, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data stored in said second data register to said input of said left most one detector, store said output of said left most one detector in a third data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a fourth instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said third data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 30

A data processing apparatus for Huffman encoding a series of multibit signed digital numbers comprising: a set of a plurality of data registers, said number stored in a first data register; a left most one detector having an input connected to said set of data registers and an output, said left most one detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which has a "1" at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply a multibit digital number equal to zero to said first input of said arithmetic logic unit, supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to subtract said second input from said first input, store said output of said arithmetic logic unit in a second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero, store data stored in said first data register in said second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was greater than or equal to zero, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data stored in said second data register to said input of said left most one detector, store said output of said left most one detector in a third data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a fourth instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said third data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 31

The data processing apparatus of claim 26, further comprising: a barrel rotator having an input connected to said set of data registers, a rotate control input and an output, said barrel rotator generating at said output a multibit digital signal corresponding to a signal at said input rotated an amount corresponding to a signal at said rotate control input; and wherein said instruction decoder is further responsive to a fifth instruction to supply data stored in said third second data register to said input of said barrel rotator, supply data stored in said third data register to said rotate control input of said barrel rotator, and store said output of said barrel rotator in a fourth data register, and wherein said instruction decoder is further responsive to a sixth instruction to supply data stored in said fourth data register to said first input of said arithmetic logic unit, supply data stored in said first data register to said second input of said arithmetic logic unit, supply data stored in said third data register to said third input of said arithmetic logic unit, control said arithmetic logic unit to output bits supplied to said first input if corresponding bits of said third input have a first digital state and to output bit supplied to said second input is corresponding bits of said third input have a second digital state opposite to said first digital state, and store said output of said arithmetic logic unit in a fifth data register.

Claim 32

An data processing system for Huffman encoding a series of multibit signed digital numbers comprising: an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a set of a plurality of data registers, said number stored in a first data register; a left most one detector having an input connected to said set of data registers and an output, said left most one detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which has a "1" at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply a multibit digital number equal to zero to said first input of said arithmetic logic unit, supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to subtract said second input from said first input, store said output of said arithmetic logic unit in a second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero, store data stored in said first data register in said second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was greater than or equal to zero, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data stored in said second data register to said input of said left most one detector, store said output of said left most one detector in a third data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a fourth instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said third data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 33

An data processing system for Huffman encoding a series of multibit signed digital numbers comprising: an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a set of a plurality of data registers, said number stored in a first data register; a left most one detector having an input connected to said set of data registers and an output, said left most one detector generating at said output a digital number corresponding to a greatest significant bit of the signal at said input which has a "1" at said input; an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input; an arithmetic logic unit having first, second and third inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first, second and third inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is less than zero; a status register connected to said status detector for storing said single bit status signal; and an instruction decoder responsive to a stream of instructions connected to said set of data registers, said left most bit change detector, said arithmetic logic unit and said status register, said instruction decoder responsive to a first instruction to supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to output data received at said first input, store said single bit status signal in said status register, and store said output of said arithmetic logic unit in said first data register, said instruction decoder responsive to a second instruction to supply a multibit digital number equal to zero to said first input of said arithmetic logic unit, supply data stored in said first data register to said first input of said arithmetic logic unit, control said arithmetic logic unit to subtract said second input from said first input, store said output of said arithmetic logic unit in a second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero, store data stored in said first data register in said second data register if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was greater than or equal to zero, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a third instruction to supply data stored in said second data register to said input of said left most one detector, store said output of said left most one detector in a third data register, and prohibit change of the state of said single bit status signal stored in said status register, said instruction decoder responsive to a fourth instruction to supply data in said first data register to said first input of said arithmetic logic unit, supply data in said third data register to said second input of said arithmetic logic unit, control said arithmetic logic unit to perform addition of data received at said first and second inputs and store said output in said first data register only if said single bit status signal stored in said status register indicates a prior output of said arithmetic logic unit was less than zero.

Claim 34

The data processing system of claim 28, wherein: said data processor circuit further includes a barrel rotator having an input connected to said set of data registers, a rotate control input and an output, said barrel rotator generating at said output a multibit digital signal corresponding to a signal at said input rotated an amount corresponding to a signal at said rotate control input; and wherein said instruction decoder is further responsive to a fifth instruction to supply data stored in said third second data register to said input of said barrel rotator, supply data stored in said third data register to said rotate control input of said barrel rotator, and store said output of said barrel rotator in a fourth data register, and wherein said instruction decoder is further responsive to a sixth instruction to supply data stored in said fourth data register to said first input of said arithmetic logic unit, supply data stored in said first data register to said second input of said arithmetic logic unit, supply data stored in said third data register to said third input of said arithmetic logic unit, control said arithmetic logic unit to output bits supplied to said first input if corresponding bits of said third input have a first digital state and to output bit supplied to said second input is corresponding bits of said third input have a second digital state opposite to said first digital state, and store said output of said arithmetic logic unit in a fifth data register.

Claim 35

The data processing system of claim 28, wherein: said data processor circuit further includes a plurality of data memories connected to said data processor circuit, an instruction memory supplying instructions to said data processor circuit, and a transfer controller connected to said data system bus, each of said data memories and said instruction memory controlling data transfer between said system memory and said plurality of data memories and between said system memory and said instruction memory.

Claim 36

The data processing system of claim 30, wherein: said data processor circuit further includes at least one additional data processor circuit identical to said data processor circuit, a plurality of additional data memories connected to each additional data processor circuit, an additional instruction memory supplying instructions to each additional data processor circuit, and said transfer controller is further connected to each of said additional data memories and each said additional instruction memory controlling data transfer between said system memory and said each of said additional data memories and between said system memory and each said additional instruction memory.

Claim 37

The data processing system of claim 31, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, each of said additional data processor circuits, each of said additional data memories, each additional instruction memory and said transfer controller are formed on a single integrated circuit.

Claim 38

The data processing system of claim 30, wherein: said data processor circuit further includes a master data processor, a plurality of master data memories connected to said master data processor, at least one master instruction memory supplying instructions to said master data processor, and said transfer controller is further connected to each of said master data memories and each said master instruction memory controlling data transfer between said system memory and said each of said master data memories and between said system memory and each said master instruction memory.

Claim 39

The data processing system of claim 33, wherein: said data processor circuit including said data processor circuit, said data memories, said instruction memories, said master data processor, each of said master data memories, each master instruction memory and said transfer controller are formed on a single integrated circuit.

Claim 40

The data processor system of claim 28, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an image display unit connected to said image memory generating a visually perceivable output of an image consisting of a plurality of pixels stored in said image memory.

Claim 41

The data processor system of claim 35, further comprising: a palette forming a connection between said image memory and said image display unit, said palette transforming pixels recalled from said image memory into video signals driving said image display unit; and wherein said data processor circuit further includes a frame controller connected to said palette controlling said palette transformation of pixels into video signals.

Claim 42

The data processor system of claim 28, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: a printer connected to said image memory generating a printed output of an image consisting of a plurality of pixels stored in said image memory.

Claim 43

The data processor system of claim 37, wherein: said printer consists of a color printer.

Claim 44

The data processor system of claim 37, further comprising: a printer controller forming a connection between said image memory and said printer, said printer controller transforming pixels recalled from said image memory into print signals driving said printer; and wherein said data processor circuit further includes a frame controller connected to said print controller controlling said print controller transformation of pixels into print signals.

Claim 45

The data processor system of claim 28, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and said data processor system further comprising: an imaging device connected to said image memory generating an image signal input.

Claim 46

The data processor system of claim 40, further comprising: an image capture controller forming a connection between said imaging device and said image memory, said image capture controller transforming said image signal into pixels supplied for storage in said image memory; and wherein said data processor circuit further includes a frame controller connected to said image capture controller controlling said image capture controller transformation of said image signal into pixels.

Claim 47

The data processor system of claim 28, further comprising: a modem connected to said data system bus and to a communications line.

Claim 48

The data processor system of claim 28, further comprising: a host processing system connected to said data system bus.

Claim 49

The data processor system of claim 43, further comprising: a host system bus connected to said host processing system transferring data and addresses; and at least one host peripheral connected to said host system bus.

Claim 50

The method of Huffman encoding of claim 1, wherein: said step of detecting said bit position of said greatest significant bit that differs from said most significant bit of said next multibit signed digital number includes forming a bit position multibit digital number having a value equal to a number of bit positions from said most significant bit of said next multibit signed digital number to said greatest significant bit that differs from said most significant bit of said next multibit signed digital number; and said step of generating said data size digital number includes forming said data size digital number having a value equal to said value of said bit position multibit digital number.

Claim 51

The method of Huffman encoding of claim 2, wherein: said step of detecting said bit position of said greatest significant "1" bit of said absolute value of said next multibit signed digital number includes forming a bit position multibit digital number having a value equal to a number of bit positions from said most significant bit of said absolute value of said next multibit signed digital number to said greatest significant "1" bit of said absolute value of said next multibit signed digital number; and said step of generating said data size digital number includes forming said data size digital number having a value equal to said value of said bit position multibit digital number.

Claim 52

The data processing apparatus of claim 7, wherein: said left most bit change detector generates at said output said digital number having a value equal to a number of bit positions from said most significant bit of said signal at said input to said greatest significant bit that differs from said most significant bit of said signal at said input.

Claim 53

The data processing system of claim 9, wherein: said left most bit change detector generates at said output said digital number having a value equal to a number of bit positions from said most significant bit of said signal at said input to said greatest significant bit that differs from said most significant bit of said signal at said input.

Claim 54

The data processing apparatus of claim 26, wherein: said left most one detector generates at said output said digital number having a value equal to a number of bit positions from said most significant bit of said signal at said input to said greatest significant bit of the signal at said input which has a "1" at said input.

Claim 55

The data processing system of claim 28, wherein: said left most one detector generates at said output said digital number having a value equal to a number of bit positions from said most significant bit of said signal at said input to said greatest significant bit of the signal at said input which has a "1" at said input.