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US5513123A Expired / Lapsed US ⏱️ 0.0 years remaining

Non-scan design-for-testability of RT-level data paths

Assignee: NEC Corp
•
Filing: 1994-06-30
•
Granted: 1996-04-30
•
Expires: 2014-06-30
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Abstract

Abstract Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.

Inventors

  • 👤 Sujit Dey
  • 👤 Miodrag Potkonjak

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 13:19
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2226; G06F30/00; G06F30/30

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 64 words
A method of non-scan design-for-testability of circuits comprising the steps of: defining a circuit to be synthesized functionally in terms of a register-transfer level data path; modifying the register-transfer level data path by adding observable points and controllable points to render the circuit to be k-level controllable and/or observable; and synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
Claim 2
Independent Claim 64 words
A method of non-scan design-for-testability of circuits comprising the steps of: defining a circuit to be synthesized functionally in terms of a register-transfer level data path; modifying the register-transfer level data path by adding observable points and controllable points to render the circuit to be k-level controllable and/or observable; and synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
Claim 3
Dependent Claim 26 words
A method of non-scan design-for-testability of circuits as set forth in claim 1 where said modifying the register-transfer level data path comprises a direct non-scan method.
Claim 4
Dependent Claim 27 words
A method of non-scan design-for-testability of circuits as set forth in claim 1 where said modifying the register-transfer level data path comprises a register-file based non-scan method.
Claim 5
Dependent Claim 32 words
A method of non-scan design-for-testability of circuits as set forth in claim 1 where said modifying the register-transfer level data path comprises making loops in the register-transfer level data path k-level controllable/observable.
Claim 6
Dependent Claim 27 words
A method of non-scan design-for-testability of circuits as set forth in claim 4 where said making loops k-level controllable/observable includes performing algorithm add_test_points() to minimize hardware costs.
Claim 7
Dependent Claim 23 words
A method of non-scan design-for-testability of circuits as set forth in claim 5 where said performing algorithm add test points() uses dual points.
Claim 8
Dependent Claim 26 words
A method of non-scan design-for-testability of circuits as set forth in claim 4 where the values of k for k-level controllable and k-level observable are different.
Claim 9
Independent Claim 67 words
A method of non-scan design-for-testability of circuits comprising the steps of: defining a circuit to be synthesized functionally in terms of a register-transfer level data path; modifying the register-transfer level data path by adding constants for providing observable points and controllable points to render the circuit to be k-level controllable and/or observable; and synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
Claim 10
Independent Claim 67 words
A method of non-scan design-for-testability of circuits comprising the steps of: defining a circuit to be synthesized functionally in terms of a register-transfer level data path; modifying the register-transfer level data path by adding constants for providing observable points and controllable points to render the circuit to be k-level controllable and/or observable; and synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
Claim 11
Dependent Claim 26 words
A method of non-scan design-for-testability of circuits as set forth in claim 8 where said modifying the register-transfer level data path comprises a direct non-scan method.
Claim 12
Dependent Claim 27 words
A method of non-scan design-for-testability of circuits as set forth in claim 8 where said modifying the register-transfer level data path comprises a register-file based non-scan method.
Claim 13
Dependent Claim 31 words
Method of non-scan design-for-testability of circuits as set forth in claim 8 where said modifying the register-transfer level data path comprises making loops in the register-transfer level data path k-level controllable/observable.
Claim 14
Dependent Claim 27 words
A method of non-scan design-for-testability of circuits as set forth in claim 11 where said making loops k-level controllable/observable includes performing algorithm add_test_points() to minimize hardware costs.
Claim 15
Dependent Claim 21 words
A method of non-scan design-for-testability of circuits as set forth in claim 12 where said performing algorithm add_test_points() uses dual points.
Claim 16
Dependent Claim 26 words
A method of non-scan design-for-testability of circuits as set forth in claim 11 where the values of k for k-level controllable, and k-level observable are different.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-04-30 1999-10-30 2000-04-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-04-30 2003-10-30 2004-04-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-04-30 2007-10-30 2008-04-30 $7700.00 Window Closed / Lapsed

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