Apparatus for tracing activity on a bus of an in-circuit emulator

Claim 2

In a data processing system including a microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a control line; an event detector connected to said microprocessor bus and to said control line; arrival of a first event on said microprocessor bus being signified by a transition of said control line, stage 1 storage elements connected to said event detector and to said microprocessor bus; and stage 2 storage elements connected to said event detector, to said stage 1 storage elements, and to said trace bus; a method of tracing event activity on said microprocessor bus comprising steps of: A. detecting at said event detector a start of cycle event on said microprocessor bus; B. generating at said event detector a start of cycle signal with reference to said start of cycle event; C. writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; D. detecting at said event detector an end of cycle event on said microprocessor bus; E. generating at said event detector an end of cycle signal with reference to said end of cycle event; F. writing data that is stored in said stage 1 storage elements into said stage 2 storage elements in response to said end of cycle signal; G. providing a synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; and, H. combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 3

The method in accordance with claim 1 wherein said stage 2 storage elements are connected to said microprocessor bus, said method further comprising steps of: I. using said end of cycle signal to sample data from said microprocessor bus into said stage 2 storage elements.

Claim 4

The method in accordance with claim 1 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 5

The method in accordance with claim 2 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 6

A data processing system comprising: a microprocessor bus; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a control line; event detector means connected to said microprocessor bus and to said control line; arrival of a first event on said microprocessor bus being signified by a transition of said control line, stage 1 storage elements connected to said microprocessor bus and to said event detector means; and, stage 2 storage elements connected to said event detector means, to said stage 1 storage elements, and to said trace bus; said event detector means including first means for detecting a start of cycle event on said microprocessor bus; said event detector means including second means connected to said first means for generating a start of cycle signal with reference to said start of cycle event; third means connected to said second means and to said first storage elements for using said start of cycle signal to sample data from said microprocessor bus into said stage 1 storage elements; fourth means for detecting an end of cycle event on said microprocessor bus; fifth means for generating an end of cycle signal with reference to said end of cycle event; sixth means connected to said fifth means and to said stage 2 storage elements for using said end of cycle signal to sample data from said stage 1 storage elements into said stage 2 storage elements; and, seventh means connected to said synchronizing clock and to said fourth means for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 7

A data processing system comprising: a microprocessor bus; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a control line; event detector means connected to said microprocessor bus and to said control line; arrival of a first event on said microprocessor bus being signified by a transition of said control line, stage 1 storage elements connected to said microprocessor bus and to said event detector means; and, stage 2 storage elements connected to said event detector means, to said stage 1 storage elements, and to said trace bus; said event detector means including first means for detecting a start of cycle event on said microprocessor bus; said event detector means including second means connected to said first means for generating a start of cycle signal with reference to said start of cycle event; third means connected to said second means and to said first storage elements for using said start of cycle signal to sample data from said microprocessor bus into said stage 1 storage elements; fourth means for detecting an end of cycle event on said microprocessor bus; fifth means for generating an end of cycle signal with reference to said end of cycle event; sixth means connected to said fifth means and to said stage 2 storage elements for using said end of cycle signal to sample data from said stage 1 storage elements into said stage 2 storage elements; and, seventh means connected to said synchronizing clock and to said fourth means for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 8

The apparatus in accordance with claim 5 wherein said stage 2 storage elements are connected to said microprocessor bus and said sixth means includes eighth means for using said end of cycle signal to sample data from said microprocessor bus into said stage 2 storage elements.

Claim 9

The apparatus in accordance with claim 6 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 10

The apparatus in accordance with claim 5 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 11

A data processing system comprising: a microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency: a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a control line; an event detector connected to said microprocessor bus and to said control line; arrival of a first event on said microprocessor bus being signified by a transition of said control line, stage 1 storage elements connected to said microprocessor bus and to said event detector; and, stage 2 storage elements connected to said event detector and to said stage 1 storage elements: said event detector detecting a start of cycle event on said microprocessor bus; said event detector generating a start of cycle signal with reference to said start of cycle event; said stage 1 storage elements writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; said event detector detecting an end of cycle event on said microprocessor bus; said event detector generating an end of cycle signal with reference to said end of cycle event; said stage 2 storage elements writing said data from said stage 1 storage elements into said stage 2 storage elements in response to said start of cycle signal; and, a synchronizer connected to said synchronizing clock and to said event detector for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 12

A data processing system comprising: a microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency: a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a control line; an event detector connected to said microprocessor bus and to said control line; arrival of a first event on said microprocessor bus being signified by a transition of said control line, stage 1 storage elements connected to said microprocessor bus and to said event detector; and, stage 2 storage elements connected to said event detector and to said stage 1 storage elements: said event detector detecting a start of cycle event on said microprocessor bus; said event detector generating a start of cycle signal with reference to said start of cycle event; said stage 1 storage elements writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; said event detector detecting an end of cycle event on said microprocessor bus; said event detector generating an end of cycle signal with reference to said end of cycle event; said stage 2 storage elements writing said data from said stage 1 storage elements into said stage 2 storage elements in response to said start of cycle signal; and, a synchronizer connected to said synchronizing clock and to said event detector for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 13

The apparatus in accordance with claim 9 wherein said stage 2 storage elements are connected to said microprocessor bus; and, said stage 2 storage elements writes data from said microprocessor bus into said stage 2 storage elements in response to said end of cycle signal.

Claim 14

The apparatus in accordance with claim 10 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 15

The apparatus in accordance with claim 9 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 16

In a data processing system including a first microprocessor and a second microprocessor a microprocessor bus connected to said first microprocessor and to said second microprocessor; said microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; an event detector connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event associated with said first microprocessor on said microprocessor bus being signified by a transition of said first control line, arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line; stage 1 storage elements connected to said event detector and to said microprocessor bus; and stage 2 storage elements connected to said event detector, to said stage 1 storage elements, and to said trace bus; a method of tracing event activity on said microprocessor bus comprising steps of: A. detecting at said event detector a start of cycle event on said microprocessor bus; B. generating at said event detector a start of cycle signal with reference to said start of cycle event; C. writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; D. detecting at said event detector an end of cycle event on said microprocessor bus; E. generating at said event detector an end of cycle signal with reference to said end of cycle event; F. writing data that is stored in said stage 1 storage elements into said stage 2 storage elements in response to said end of cycle signal; G. providing a synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; and, H. combining said synchronizing -- clock with said end of cycle signal to generate a trace bus valid signal.

Claim 17

In a data processing system including a first microprocessor and a second microprocessor a microprocessor bus connected to said first microprocessor and to said second microprocessor; said microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; an event detector connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event associated with said first microprocessor on said microprocessor bus being signified by a transition of said first control line, arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line; stage 1 storage elements connected to said event detector and to said microprocessor bus; and stage 2 storage elements connected to said event detector, to said stage 1 storage elements, and to said trace bus; a method of tracing event activity on said microprocessor bus comprising steps of: A. detecting at said event detector a start of cycle event on said microprocessor bus; B. generating at said event detector a start of cycle signal with reference to said start of cycle event; C. writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; D. detecting at said event detector an end of cycle event on said microprocessor bus; E. generating at said event detector an end of cycle signal with reference to said end of cycle event; F. writing data that is stored in said stage 1 storage elements into said stage 2 storage elements in response to said end of cycle signal; G. providing a synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; and, H. combining said synchronizing -- clock with said end of cycle signal to generate a trace bus valid signal.

Claim 18

The method in accordance with claim 13 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 19

The method in accordance with claim 13 said stare 2 storage elements are connected to said microprocessor bus, said method further comprising steps of: I. using said end of cycle signal to sample data from said microprocessor bus into said stage 2 storage elements.

Claim 20

The method in accordance with claim 15 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 21

A data processing system comprising: a first microprocessor; a second microprocessor; a microprocessor bus; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; event detector means connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event on said microprocessor bus being signified by a transition of said first control line, arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line, stage 1 storage elements connected to said microprocessor bus and to said event detector means; stage 2 storage elements connected to said event detector means and to said stage 1 storage elements; said event detector means including first means for detecting a start of cycle event on said microprocessor bus; said event detector means including second means connected to said first means for generating a start of cycle signal with reference to said start of cycle event; third means connected to said first means and to said first storage elements for using said start of cycle signal to sample data from said microprocessor bus into said stage 1 storage elements; fourth means for detecting an end of cycle event on said microprocessor bus; fifth means for generating an end of cycle signal with reference to said end of cycle event; sixth means connected to said fifth means and to said stage 2 storage elements for using said end of cycle signal to sample data from said stage 1 storage elements into said stage 2 storage elements; and, seventh means connected to said synchronizing clock and to said fourth means for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal, said trace bus valid signal being synchronized with said bus clock.

Claim 22

A data processing system comprising: a first microprocessor; a second microprocessor; a microprocessor bus; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; event detector means connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event on said microprocessor bus being signified by a transition of said first control line, arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line, stage 1 storage elements connected to said microprocessor bus and to said event detector means; stage 2 storage elements connected to said event detector means and to said stage 1 storage elements; said event detector means including first means for detecting a start of cycle event on said microprocessor bus; said event detector means including second means connected to said first means for generating a start of cycle signal with reference to said start of cycle event; third means connected to said first means and to said first storage elements for using said start of cycle signal to sample data from said microprocessor bus into said stage 1 storage elements; fourth means for detecting an end of cycle event on said microprocessor bus; fifth means for generating an end of cycle signal with reference to said end of cycle event; sixth means connected to said fifth means and to said stage 2 storage elements for using said end of cycle signal to sample data from said stage 1 storage elements into said stage 2 storage elements; and, seventh means connected to said synchronizing clock and to said fourth means for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal, said trace bus valid signal being synchronized with said bus clock.

Claim 23

The method in accordance with claim 17 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 24

The apparatus in accordance with claim 17 wherein said sixth means includes eighth means for using said end of cycle signal to sample data from said microprocessor bus into said stage 2 storage elements.

Claim 25

The method in accordance with claim 19 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 26

A data processing system comprising: a first microprocessor; a second microprocessor; a microprocessor bus connected to said first microprocessor and to said second microprocessor; said microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a first control line; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; an event detector connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event associated with said first microprocessor on said microprocessor bus being signified by a transition of said first control line; arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line; stage 1 storage elements connected to said microprocessor bus and to said event detector; and, stage 2 storage elements connected to said event detector and to said stage 1 storage elements; said event detector detecting a start of cycle event on said microprocessor bus; said event detector generating a start of cycle signal with reference to said start of cycle event; said stage 1 storage elements writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; said event detector detecting an end of cycle event on said microprocessor bus; said event detector generating an end of cycle signal with reference to said end of cycle event; said stage 2 storage elements writing said data from said stage 1 storage elements into said stage 2 storage elements in response to said start of cycle signal; and, a synchronizer connected to said synchronizing clock and to said event detector for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 27

A data processing system comprising: a first microprocessor; a second microprocessor; a microprocessor bus connected to said first microprocessor and to said second microprocessor; said microprocessor bus having data thereon; a trace bus; a trace bus clock associated with said trace bus; said trace bus clock operating a predetermined frequency; a synchronizing clock; said synchronizing clock operating at a synchronizing clock frequency that is a multiple of said predetermined frequency; a first control line; a first control line associated with said first microprocessor; a second control line associated with said second microprocessor; an event detector connected to said microprocessor bus, to said first control line and to said second control line; arrival of a first event associated with said first microprocessor on said microprocessor bus being signified by a transition of said first control line; arrival of a second event associated with said second microprocessor on said microprocessor bus being signified by a transition of said second control line; stage 1 storage elements connected to said microprocessor bus and to said event detector; and, stage 2 storage elements connected to said event detector and to said stage 1 storage elements; said event detector detecting a start of cycle event on said microprocessor bus; said event detector generating a start of cycle signal with reference to said start of cycle event; said stage 1 storage elements writing said data on said microprocessor bus into said stage 1 storage elements in response to said start of cycle signal; said event detector detecting an end of cycle event on said microprocessor bus; said event detector generating an end of cycle signal with reference to said end of cycle event; said stage 2 storage elements writing said data from said stage 1 storage elements into said stage 2 storage elements in response to said start of cycle signal; and, a synchronizer connected to said synchronizing clock and to said event detector for combining said synchronizing clock with said end of cycle signal to generate a trace bus valid signal.

Claim 28

The method in accordance with claim 21 wherein said synchronizing clock frequency is twice said predetermined frequency.

Claim 29

The apparatus in accordance with claim 21 wherein said stage 2 storage elements are connected to microprocessor bus; and, said stage 2 storage elements writes data from said microprocessor bus into said stage 2 storage elements in response to said end of cycle signal.

Claim 30

The method in accordance with claim 23 wherein said synchronizing clock frequency is twice said predetermined frequency.