US5517441A
Expired / Lapsed
US
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Content addressable memory circuitry and method of operation
Assignee: International Business Machines Corp
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Filing: 1994-12-14
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Granted: 1996-05-14
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Expires: 2014-12-14
Abstract
Abstract Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.
Inventors
- 👤 Carl D. Dietz
- 👤 Kathryn J. Hoover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:19
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F7/00; G06F7/02
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
88 words
Content addressable memory circuitry, comprising: first circuitry for storing first information and selectively modifying a logic state of a first match line in response to a comparison between said first information and second information; second circuitry for storing third information and selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information; and third circuitry for selectively modifying said logic state of said second match line in response to said logic state of said first match line.
Claim 2
Dependent Claim
88 words
Content addressable memory circuitry, comprising: first circuitry for storing first information and selectively modifying a logic state of a first match line in response to a comparison between said first information and second information; second circuitry for storing third information and selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information; and third circuitry for selectively modifying said logic state of said second match line in response to said logic state of said first match line.
Claim 3
Dependent Claim
15 words
The circuitry of claim 1 and further comprising circuitry for selectively disabling said third circuitry.
Claim 4
Dependent Claim
37 words
The circuitry of claim 1 and further comprising fourth circuitry for storing fifth information and selectively modifying a logic state of a third match line in response to a comparison between said fifth information and sixth information.
Claim 5
Dependent Claim
32 words
The circuitry of claim 3 and further comprising fifth circuitry for selectively modifying said logic state of said second match line in response to said logic state of said third match line.
Claim 6
Dependent Claim
15 words
The circuitry of claim 4 and further comprising circuitry for selectively disabling said fifth circuitry.
Claim 7
Dependent Claim
18 words
The circuitry of claim 3 wherein said sixth information is available for said comparison before said fourth information.
Claim 8
Dependent Claim
18 words
The circuitry of claim 1 wherein said second information is available for said comparison before said fourth information.
Claim 9
Dependent Claim
15 words
The circuitry of claim 1 wherein said first and second circuitry are identical in design.
Claim 10
Dependent Claim
13 words
The circuitry of claim 8 wherein said first and second circuitry are cascadable.
Claim 11
Dependent Claim
17 words
The circuitry of claim 9 wherein said first and second circuitry are coupled together in a sequence.
Claim 12
Dependent Claim
17 words
The circuitry of claim 1 and further comprising circuitry for precharging said first and second match lines.
Claim 13
Dependent Claim
54 words
The circuitry of claim 11 wherein said first circuitry is operable to selectively modify said logic state of said first match line by selectively discharging said first match line, and wherein said second circuitry is operable to selectively modify said logic state of said second match line by selectively discharging said second match line.
Claim 14
Dependent Claim
15 words
The circuitry of claim 1 wherein said first circuitry comprises first content addressable memory circuitry.
Claim 15
Dependent Claim
15 words
The circuitry of claim 13 wherein said second circuitry comprises second content addressable memory circuitry.
Claim 16
Independent Claim
84 words
A method of operating content addressable memory circuitry, comprising the steps of: storing first information; selectively modifying a logic state of a first match line in response to a comparison between said first information and second information; storing third information; selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information; and selectively modifying said logic state of said second match line in response to said logic state of said first match line.
Claim 17
Independent Claim
84 words
A method of operating content addressable memory circuitry, comprising the steps of: storing first information; selectively modifying a logic state of a first match line in response to a comparison between said first information and second information; storing third information; selectively modifying a logic state of a second match line in response to a comparison between said third information and fourth information; and selectively modifying said logic state of said second match line in response to said logic state of said first match line.
Claim 18
Dependent Claim
37 words
The method of claim 15 and further comprising the steps of: storing fifth information; and selectively modifying a logic state of a third match line in response to a comparison between said fifth information and sixth information.
Claim 19
Dependent Claim
32 words
The method of claim 16 and further comprising the step of selectively modifying said logic state of said second match line in response to said logic state of said third match line.
Claim 20
Dependent Claim
18 words
The method of claim 16 wherein said sixth information is available for said comparison before said fourth information.
Claim 21
Dependent Claim
18 words
The method of claim 15 wherein said second information is available for said comparison before said fourth information.
Claim 22
Dependent Claim
18 words
The method of claim 15 and further comprising the step of precharging said first and second match lines.
Claim 23
Dependent Claim
54 words
The method of claim 20 wherein said step of selectively modifying said logic state of said first match line comprises the step of selectively discharging said first match line, and wherein said second circuitry is operable to selectively modify said logic state of said second match line by selectively discharging said second match line.
References Cited (Backward Citations)
US4823313A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |