Pipeline processor for processing instructions having a data dependence relationship

Claim 2

A pipeline processor for carrying out pipeline processing of instructions to be input, which undergo a plurality of stages including an execution stage, comprising: an arithmetic unit having a first stage arithmetic means for executing an arithmetic operation in the execution stage and a second stage arithmetic means for executing an arithmetic operation of an instruction in a stage subsequent to the execution, the arithmetic unit being provided for pipelining a first instruction and a second instruction to be executed next to the first instruction; data dependence detecting means for detecting a data dependence relationship between the first instruction and the second instruction; and control means for outputting a control signal when the data dependence detecting means detects the presence of the data dependence relationship between the first instruction and the second instruction, wherein when the control signal is output from the control means, in the arithmetic unit, the arithmetic operation of the second instruction is not executed in the execution stage but is executed by the second stage arithmetic means in the stage subsequent to the execution stage.

Claim 3

A pipeline processor according to claim 1 wherein a time for executing an arithmetic operation of the first instruction is equal to or longer than a time for executing an arithmetic operation of the second instruction.

Claim 4

A pipeline processor according to claim 2, wherein the first instruction is a load instruction.

Claim 5

A pipeline processor according to claim 3, wherein said stage arithmetic means is write stage arithmetic means for executing the operation of the second instruction in a write stage subsequent to an execution stage of the second instruction.

Claim 6

A pipeline processor according to claim 2, wherein said stage arithmetic means is memory stage arithmetic means for executing the operation of the second instruction in a memory stage subsequent to an execution stage of the second instruction.

Claim 7

A pipeline processor according to claim 2, wherein said stage arithmetic means is write stage arithmetic means for executing the operation of the second instruction in a write stage subsequent to an execution stage of the second instruction.

Claim 8

A pipeline processor according to claim 1, wherein said stage arithmetic means is memory stage arithmetic means for executing the operation of the second instruction in a memory stage subsequent to an execution stage of the second instruction.

Claim 9

A pipeline processor according to claim 1, wherein said stage arithmetic means is write stage arithmetic means for executing the operation of the second instruction in a write stage subsequent to an execution stage of the second instruction.

Claim 10

A pipeline processor for carrying out pipeline processing of instructions to be input, which undergo a plurality of stages including an execution stage, comprising: a first arithmetic unit, having a first stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage, for executing a first instruction; a second arithmetic unit having a second stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage and a third stage arithmetic means for executing an arithmetic operation of an instruction in a stage subsequent to the execution stage, the second arithmetic unit being provided for executing the second instruction to be executed next to the first instruction simultaneously with the execution of the first instruction; data dependence detecting means for detecting the presence of a data dependence relationship between the first instruction and the second instruction; and control means for outputting a control signal when the data dependence detecting means detects the presence of the data dependence relationship between the first Instruction and the second instruction; wherein when the control signal is output from the control means, in the second arithmetic unit, the arithmetic operation of the second instruction is not executed in the execution stage but is executed by the third stage arithmetic means In a stage subsequent to the execution stage.

Claim 11

A pipeline processor for carrying out pipeline processing of instructions to be input, which undergo a plurality of stages including an execution stage, comprising: a first arithmetic unit, having a first stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage, for executing a first instruction; a second arithmetic unit having a second stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage and a third stage arithmetic means for executing an arithmetic operation of an instruction in a stage subsequent to the execution stage, the second arithmetic unit being provided for executing the second instruction to be executed next to the first instruction simultaneously with the execution of the first instruction; data dependence detecting means for detecting the presence of a data dependence relationship between the first instruction and the second instruction; and control means for outputting a control signal when the data dependence detecting means detects the presence of the data dependence relationship between the first Instruction and the second instruction; wherein when the control signal is output from the control means, in the second arithmetic unit, the arithmetic operation of the second instruction is not executed in the execution stage but is executed by the third stage arithmetic means In a stage subsequent to the execution stage.

Claim 12

A pipeline processor according to claim 9, wherein a time for executing an arithmetic operation of the first instruction is equal to or longer than a time for executing an arithmetic operation of the second instruction.

Claim 13

A pipeline processor according to claim 10, wherein the first instruction is a load instruction.

Claim 14

A pipeline processor according to claim 11, wherein said stage arithmetic means is write stage arithmetic means for executing the operation of the second instruction in a write stage subsequent to an execution stage of the second instruction.

Claim 15

A pipeline processor according to claim 10, wherein said stage arithmetic means is memory stage arithmetic means for executing the operation of the second instruction in a memory stage subsequent to an execution stage of the second instruction.

Claim 16

A pipeline processor according to claim 10, wherein said stage arithmetic means is write stage arithmetic means for executing the operation of the second instruction in a write stage subsequent to an execution stage of the second instruction.

Claim 17

A pipeline processor for simultaneously processing a load instruction and an arithmetic instruction to be executed next to the load instruction both of which undergo a plurality of stages including an execution stage, comprising: a memory device for storing data; a register file for holding data read out from the memory device according to a load instruction; a first arithmetic unit having a first stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage, said first arithmetic unit for processing a load instruction; a second arithmetic unit for processing an arithmetic instruction, said second arithmetic unit having a second stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage; a third stage arithmetic means for executing an arithmetic operation of an instruction in a stage subsequent to an execution stage; data dependence detecting means, which receives the load instruction and the arithmetic instruction, for detecting whether the arithmetic instruction uses the data read out from the memory device according to the load instruction; and control means for outputting a control signal when the data dependence detecting means detects that the arithmetic instruction uses the data read out from the memory device according to the load instruction, wherein when no control signal is output from the control means, the arithmetic operation of said arithmetic instruction is executed in the execution stage by the second stage arithmetic means, and wherein when a control signal is output from the control means, the data read out from the memory device according to the load instruction is input to the third stage arithmetic means so that the arithmetic operation of said arithmetic instruction is executed in the stage subsequent to the execution stage by the third stage arithmetic means.

Claim 18

A pipeline processor for simultaneously processing a load instruction and an arithmetic instruction to be executed next to the load instruction both of which undergo a plurality of stages including an execution stage, comprising: a memory device for storing data; a register file for holding data read out from the memory device according to a load instruction; a first arithmetic unit having a first stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage, said first arithmetic unit for processing a load instruction; a second arithmetic unit for processing an arithmetic instruction, said second arithmetic unit having a second stage arithmetic means for executing an arithmetic operation of an instruction in the execution stage; a third stage arithmetic means for executing an arithmetic operation of an instruction in a stage subsequent to an execution stage; data dependence detecting means, which receives the load instruction and the arithmetic instruction, for detecting whether the arithmetic instruction uses the data read out from the memory device according to the load instruction; and control means for outputting a control signal when the data dependence detecting means detects that the arithmetic instruction uses the data read out from the memory device according to the load instruction, wherein when no control signal is output from the control means, the arithmetic operation of said arithmetic instruction is executed in the execution stage by the second stage arithmetic means, and wherein when a control signal is output from the control means, the data read out from the memory device according to the load instruction is input to the third stage arithmetic means so that the arithmetic operation of said arithmetic instruction is executed in the stage subsequent to the execution stage by the third stage arithmetic means.