US5523243A
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Method of fabricating a triple heterojunction bipolar transistor
Assignee: International Business Machines Corp
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Filing: 1994-06-08
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Granted: 1996-06-04
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Expires: 2014-06-08
Abstract
Abstract A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N + silicon, an N - silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N - silicon layer. The THBT base is layer of P + SiGe grown on the superlattice. The THBT Emitter is a second Si/SiGe Superlattice grown on the base layer. An N - silicon layer is grown on the emitter superlattice. A layer of N + GaP grown on that N - Si layer. The base is formed, first, by etching a rectangular groove through the emitter, ion implanting dopant into the base layer to form an extrinsic base, etching a V shaped groove into the extrinsic base and, then, filling the grooved base with doped polysilicon.
Inventors
- 👤 S. Noor Mohammad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:28
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821; H10D10/891; Y; Y10; Y10S; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
114 words
A method of fabricating a Heterojunction Bipolar Transistor (HBT) comprising the steps of: a) growing a first superlattice on a first layer of a first semiconductor material; b) growing a base layer of a second semiconductor material on said superlattice; c) growing a second superlattice on said base layer; d) growing a top layer of said first semiconductor material on said second superlattice; and e) defining an intrinsic base in said base layer comprising the steps of: i) etching a rectangular groove through said top layer and said second superlattice to said base layer, ii) ion implanting a dopant into said base layer through said groove, and iii) providing emitter, collector and base contacts.
Claim 2
Independent Claim
114 words
A method of fabricating a Heterojunction Bipolar Transistor (HBT) comprising the steps of: a) growing a first superlattice on a first layer of a first semiconductor material; b) growing a base layer of a second semiconductor material on said superlattice; c) growing a second superlattice on said base layer; d) growing a top layer of said first semiconductor material on said second superlattice; and e) defining an intrinsic base in said base layer comprising the steps of: i) etching a rectangular groove through said top layer and said second superlattice to said base layer, ii) ion implanting a dopant into said base layer through said groove, and iii) providing emitter, collector and base contacts.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein the step (a) of growing a first superlattice wherein said first layer of said first semiconductor material is grown on a substrate of said first semiconductor material.
Claim 4
Dependent Claim
61 words
The method of claim 2 wherein the step (iii) of providing emitter, collector and base contacts comprises the steps of: a) etching a V groove into said base layer; b) filling said V groove with polysilicon; and c) depositing metal onto a bottom surface of said substrate, a top surface of said second layer and a top surface of said polysilicon.
Claim 5
Dependent Claim
68 words
The method of claim 1 wherein the step (a) of growing a first superlattice comprises the steps of: i) growing a first superlattice layer of said second semiconductor material on said first layer; ii) growing a second superlattice layer of said first semiconductor material on said first superlattice layer; and iii) repeating steps i and ii until at least two and less than eight superlattice layers are grown.
Claim 6
Dependent Claim
69 words
The method of claim 1 wherein the step (c) of growing a second superlattice layer comprises the steps of: i) growing a first superlattice layer of said first semiconductor material on said base layer; ii) growing a second superlattice layer of said second semiconductor material on said first superlattice layer; and iii) repeating steps i and ii until at least two and less than eight superlattice layers are grown.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said first semiconductor material is silicon and said second semiconductor material is SiGe.
Claim 8
Independent Claim
146 words
A method of fabricating a Heterojunction Bipolar Transistor (HBT) comprising the steps of: a) growing a first superlattice on a first layer of a first semiconductor material, said first layer being grown on a substrate of said first semiconductor material; b) growing a base layer of a second semiconductor material on said superlattice; c) growing a second superlattice on said base layer; d) growing a top layer of said first semiconductor material on said second superlattice; e) growing a layer of a third semiconductor material on said top layer; and f) defining an intrinsic base in said base layer comprising the steps of: i) etching a rectangular groove through said layer of third semiconductor material, said second layer and said second superlattice to said base layer, ii) ion implanting a dopant into said base layer through said groove, and iii) providing emitter, collector and base contacts.
Claim 9
Independent Claim
146 words
A method of fabricating a Heterojunction Bipolar Transistor (HBT) comprising the steps of: a) growing a first superlattice on a first layer of a first semiconductor material, said first layer being grown on a substrate of said first semiconductor material; b) growing a base layer of a second semiconductor material on said superlattice; c) growing a second superlattice on said base layer; d) growing a top layer of said first semiconductor material on said second superlattice; e) growing a layer of a third semiconductor material on said top layer; and f) defining an intrinsic base in said base layer comprising the steps of: i) etching a rectangular groove through said layer of third semiconductor material, said second layer and said second superlattice to said base layer, ii) ion implanting a dopant into said base layer through said groove, and iii) providing emitter, collector and base contacts.
Claim 10
Dependent Claim
61 words
The method of claim 7 wherein the step (iii) of providing emitter, collector and base contacts comprises the steps of: a) etching a V groove in said base layer; b) filling said V groove with polysilicon; and c) depositing metal onto a bottom surface of said substrate, a top surface of said second layer and a top surface of said polysilicon.
Claim 11
Dependent Claim
25 words
The method of claim 7 wherein said first semiconductor material is silicon, said second semiconductor material is SiGe and said third semiconductor material is GaP.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |