Controlling synchronous serial access to a multiport memory

Claim 2

An integrated circuit, responsive to an external continuous clock signal and an external enable signal comprising: a. a plurality of memory cells; b. parallel means for random access to the plurality of memory cells; and c. serial means for synchronous serial access to the plurality of memory cells, wherein synchronous serial access is selectively responsive to the external continuous clock signal received by the serial means and the external clock enable signal; and d. said serial means further responsive to a data signal for storing a bit in a selected cell and including delay means coupled for delaying the data signal to internally synchronize the data signal and the external continuous clock.

Claim 3

The integrated circuit of claim 1 wherein the serial means comprises: a. sequencing means, responsive to a serial access signal, for selecting a next cell in sequence for accessing; and b. timing means for providing the serial access signal in response to the clock signal, an enable signal, and a disable signal, wherein the serial access signal is provided between receiving the enable signal and receiving the disable signal.

Claim 4

The integrated circuit of claim 2 wherein the enable signal is received by the timing means on a conductor and the disable signal is received by the timing means on the conductor.

Claim 5

The integrated circuit of claim 2 wherein the enable signal comprises a first logic level of a control signal and the disable signal comprises a second logic level of the control signal.

Claim 6

The integrated circuit of claim 2 wherein the timing means comprises a circuit for providing the serial access signal responsive to a logic AND of the clock signal, the enable signal, and the disable signal.

Claim 7

The integrated circuit of claim 2 wherein the sequencing means comprises a counter for selecting the next cell in sequence, the counter responsive to the serial access signal for counting when the serial access signal is received.

Claim 8

The integrated circuit of claim 2 wherein the sequencing means comprises a counter responsive to the clock signal for counting, responsive to the disable signal for disabling counting, and responsive to the enable signal for enabling counting.

Claim 9

The integrated circuit of claim 2 wherein the sequencing means comprises a shift register for storing a pattern and for providing a shift output signal responsive to the pattern, the shift output signal for selecting the next cell in sequence, the shift register responsive to the serial access signal for shifting the pattern when the serial access signal is received.

Claim 10

The integrated circuit of claim 2 wherein the sequencing means comprises a shift register for storing a pattern, for shifting the pattern, and for providing a shift output signal responsive to the pattern, the shift output signal used to select the next cell in sequence, the shift register responsive to the clock signal for shifting, responsive to the disable signal for disabling shifting, and responsive to the enable signal for enabling shifting.

Claim 13

An integrated circuit, responsive to an external continuous clock signal and an external clock enable signal, comprising: a. a plurality of memory cells arranged in at least one row; b. parallel means for random access to the plurality; c. transfer means, comprising a register, for transferring, in a first direction, the content of the register to the row, and for transferring, in a second direction, the content of the row to the register, the transfer means responsive to a direction signal for enabling one of the first direction and the second direction; d. serial means for synchronous serial access to the register, wherein synchronous serial access is selectively responsive to the external continuous clock signal and the external clock enable signal received by the serial means, the serial means responsive to the direction signal for enabling signalling on a first conductor used for bidirectional signalling, signalling when enabled being in one of two signalling directions; and e. said serial means further responsive to a data signal for storing a bit in a selected cell and including delay means coupled for delaying the data signal to internally synchronize the data signal and the external continuous clock.

Claim 14

An integrated circuit, responsive to an external continuous clock signal and an external clock enable signal, comprising: a. a plurality of memory cells arranged in at least one row; b. parallel means for random access to the plurality; c. transfer means, comprising a register, for transferring, in a first direction, the content of the register to the row, and for transferring, in a second direction, the content of the row to the register, the transfer means responsive to a direction signal for enabling one of the first direction and the second direction; d. serial means for synchronous serial access to the register, wherein synchronous serial access is selectively responsive to the external continuous clock signal and the external clock enable signal received by the serial means, the serial means responsive to the direction signal for enabling signalling on a first conductor used for bidirectional signalling, signalling when enabled being in one of two signalling directions; and e. said serial means further responsive to a data signal for storing a bit in a selected cell and including delay means coupled for delaying the data signal to internally synchronize the data signal and the external continuous clock.

Claim 15

The integrated circuit of claim 11 wherein the direction control means comprises: a. a mode register for providing and maintaining the direction signal; and b. a control circuit, coupled to the mode register, for changing the content of the mode register.

Claim 16

The integrated circuit of claim 12 wherein: a. the transfer means is responsive to a transfer signal for transferring, in a first direction, the content of the register to the row, and for transferring, in a second direction, the content of the row to the register; and b. the serial means comprises a buffer having a buffered output coupled to the first conductor, the buffer responsive to the transfer signal for enabling the buffered output.

Claim 17

The integrated circuit of claim 12 wherein the serial means comprises a buffer having a buffered output coupled to the first conductor, the buffer responsive to the clock signal for enabling the buffered output.

Claim 18

The integrated circuit of claim 11 wherein the serial means comprises: a. sequencing means, responsive to a serial access signal, for selecting a next cell in sequence for accessing; and b. timing means for providing the serial access signal in response to the clock signal, an enable signal, and a disable signal, wherein the serial access signal is provided between receiving the enable signal and receiving the disable signal.

Claim 19

The integrated circuit of claim 15 wherein the enable signal is received by the timing means on a second conductor and the disable signal is received by the timing means on the second conductor.

Claim 20

The integrated circuit of claim 15 wherein the enable signal comprises a first logic level of a control signal and the disable signal comprises a second logic level of the control signal.

Claim 21

The integrated circuit of claim 15 wherein the timing means comprises a circuit for providing the serial access signal responsive to a logic AND of the clock signal, the enable signal, and the disable signal.

Claim 22

The integrated circuit of claim 15 wherein the sequencing means comprises a counter for selecting the next cell in sequence, the counter responsive to the serial access signal for counting when the serial access signal is received.

Claim 23

The integrated circuit of claim 15 wherein the sequencing means comprises a counter responsive to the clock signal for counting, responsive to the disable signal for disabling counting, and responsive to the enable signal for enabling counting.

Claim 24

The integrated circuit of claim 15 wherein the sequencing means comprises a shift register for storing a pattern and for providing a shift output signal responsive to the pattern, the shift output signal for selecting the next cell in sequence, the shift register responsive to the serial access signal for shifting the pattern when the serial access signal is received.

Claim 25

The integrated circuit of claim 15 wherein the sequencing means comprises a shift register for storing a pattern, for shifting the pattern, and for providing a shift output signal responsive to the pattern, the shift output signal used to select the next cell in sequence, the shift register responsive to the clock signal for shifting, responsive to the disable signal for disabling shifting, and responsive to the enable signal for enabling shifting.