Semiconductor integrated circuit

Claim 1

A semiconductor integrated circuit comprising: a signal input terminal; a power supply voltage terminal to which a power supply voltage is applied; a reference voltage terminal to which a ground voltage is applied; a first PMOS transistor having a drain, a gate connected to said signal input terminal, and a source connected to said power supply voltage terminal; a second PMOS transistor having a gate and a drain being mutually connected to each other, and a source connected to said drain of said first transistor; a third PMOS transistor having a gate connected to said drain of said second transistor, a source connected to said power supply voltage terminal, and a drain connected to the drain of said first transistor; an NMOS transistor having a gate connected to said power supply voltage terminal, a drain connected to said drain of said second PMOS transistor, and a source connected to said reference voltage terminal; an internal circuit connected to said drain of said NMOS transistor; a first overvoltage absorption element, connected between said reference voltage terminal and said signal input terminal, for absorbing an overvoltage applied to said signal input terminal; and a second overvoltage absorption element, connected between said signal input terminal and said power supply voltage terminal, for absorbing an overvoltage applied to said signal input terminal wherein when on-resistance of said first PMOS transistor is RP1(ON), on-resistance of said second PMOS transistor is RP2(ON), on-resistance of said third PMOS transistor is RP3(ON), on-resistance of said NMOS transistor is RN1(ON), and said power supply voltage is VCC, the following relation is set to be established: RP1(ON)+RP2(ON)<RN1(ON)<RP3(ON)+RP2(ON), and a circuit threshold voltage of said internal circuit is substantially the same a 1/2 VCC.