US5528635A
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Synchronization detecting circuit
Assignee: Ando Electric Co Ltd
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Filing: 1995-06-21
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Granted: 1996-06-18
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Expires: 2015-06-21
Abstract
Abstract A testing device is provided to test performance of transmission systems such as communication devices and transmission lines by transmitting and receiving specific patterns called pseudo-random patterns (i.e., PN patterns). A receiver unit of the testing device provides a synchronization detecting circuit. The synchronization detecting circuit comprises a pseudo-random-pattern creating circuit, a first coincidence detecting block, a second coincidence detecting block and an OR circuit. The first coincidence detecting block detects coincidence between a receiving-data input, a first detected-pattern input and a pseudo-random pattern created by the pseudo-random-pattern creating circuit so as to produce a first coincidence detecting signal. The second coincidence detecting block detects coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal. The first and second coincidence detecting signals are applied to the OR circuit, by which a synchronous detection signal is produced. Thus, synchronization between the receiving-data input and pseudo-random pattern is detected by the synchronous detection signal. Incidentally, each of the first and second detected-pattern inputs receives the pseudo-random pattern transmitted thereto through the transmission system; and the second detected-pattern input is delayed behind the first detected-pattern input by `m` bits (where `m` is an integer which is determined in advance).
Inventors
- 👤 Keiji Negi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 01:26
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/043; H04L1/00; H04L1/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
103 words
A synchronization detecting circuit comprising: pseudo-random-pattern creating means for creating a pseudo-random pattern; first coincidence detecting block for detecting coincidence between a receiving-data input, a first detected-pattern input and the pseudo-random pattern so as to produce a first coincidence detecting signal; second coincidence detecting block for detecting coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal; and means for producing a synchronous detection signal based on the first and second coincidence detecting signals, whereby synchronization between the pseudo-random pattern and the receiving-data input is detected by the synchronous detection signal.
Claim 2
Dependent Claim
103 words
A synchronization detecting circuit comprising: pseudo-random-pattern creating means for creating a pseudo-random pattern; first coincidence detecting block for detecting coincidence between a receiving-data input, a first detected-pattern input and the pseudo-random pattern so as to produce a first coincidence detecting signal; second coincidence detecting block for detecting coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal; and means for producing a synchronous detection signal based on the first and second coincidence detecting signals, whereby synchronization between the pseudo-random pattern and the receiving-data input is detected by the synchronous detection signal.
Claim 3
Dependent Claim
33 words
A synchronization detecting circuit as defined in claim 1 wherein the means produces the synchronous detection signal when either the first coincidence detecting signal or the second coincidence detecting signal is applied thereto.
Claim 4
Dependent Claim
52 words
A synchronization detecting circuit as defined in claim 1 wherein each of the first and second detected-pattern inputs receives the pseudo-random pattern transmitted thereto through transmission means and the second detected-pattern input is delayed behind the first detected-pattern input by `m` bits (where `m` is an integer which is determined in advance).
Claim 5
Dependent Claim
205 words
A synchronization detecting circuit comprising: pseudo-random-pattern creating means for creating a pseudo-random pattern; first comparison means for comparing a receiving-data input and a first detected-pattern input so as to produce a detection pulse; first pattern comparison means for comparing the pseudo-random pattern and the first detected-pattern input so as to produce a detection pulse; first coincidence detecting means for detecting coincidence between the detection pulse of the first comparison means and the detection pulse of the first pattern comparison means so as to produce a first coincidence detecting signal; second comparison means for comparing the receiving-data input and a second detected-pattern input so as to produce a detection pulse; second pattern comparison means for comparing the pseudo-random pattern and the second detected-pattern input so as to produce a detection pulse; second coincidence detecting means for detecting coincidence between the detection pulse of the second comparison means and the detection pulse of the second pattern comparison means so as to produce a second coincidence detecting signal; and means for producing a logical OR between the first and second coincidence detecting signals so as to produce a synchronous detection signal, whereby synchronization between the receiving-data input and the pseudo-random pattern is detected by the synchronous detection signal.
Claim 6
Dependent Claim
205 words
A synchronization detecting circuit comprising: pseudo-random-pattern creating means for creating a pseudo-random pattern; first comparison means for comparing a receiving-data input and a first detected-pattern input so as to produce a detection pulse; first pattern comparison means for comparing the pseudo-random pattern and the first detected-pattern input so as to produce a detection pulse; first coincidence detecting means for detecting coincidence between the detection pulse of the first comparison means and the detection pulse of the first pattern comparison means so as to produce a first coincidence detecting signal; second comparison means for comparing the receiving-data input and a second detected-pattern input so as to produce a detection pulse; second pattern comparison means for comparing the pseudo-random pattern and the second detected-pattern input so as to produce a detection pulse; second coincidence detecting means for detecting coincidence between the detection pulse of the second comparison means and the detection pulse of the second pattern comparison means so as to produce a second coincidence detecting signal; and means for producing a logical OR between the first and second coincidence detecting signals so as to produce a synchronous detection signal, whereby synchronization between the receiving-data input and the pseudo-random pattern is detected by the synchronous detection signal.
Claim 7
Dependent Claim
52 words
A synchronization detecting circuit as defined in claim 4 wherein each of the first and second detected-pattern inputs receives the pseudo-random pattern transmitted thereto through transmission means and the second detected-pattern input is delayed behind the first detected-pattern input by `m` bits (where `m` is an integer which is determined in advance).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |