Abstract The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits. The signal generating circuit output maintains the gate voltage of each of the input transistors near the edge of conduction when receiving the signal that the voltage of the respective row line is to be raised. Otherwise the signal generating circuit maintains the gate voltage at ground potential.
An integrated circuit, comprising: a plurality of row decoder-driver circuits each for raising the voltage of a respective row line, each of the plurality of row decoder-driver circuits having an address decoder capable of receiving a plurality of address bits, the plurality address bits when decoded by the address decoder identify one of the plurality of row decoder-drivers to provide an output, each of the plurality of row decoder-drivers having an input transistor having a gate, the input transistor having a conduction path coupled between a power supply node and the address decoder; and a signal generating circuit, the signal generating circuit for receiving a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit, the signal generating circuit providing an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits, the output maintains the gate of each input transistor near the edge of conduction of said input transistor.
Claim 2
Dependent Claim
166 words
An integrated circuit, comprising: a plurality of row decoder-driver circuits each for raising the voltage of a respective row line, each of the plurality of row decoder-driver circuits having an address decoder capable of receiving a plurality of address bits, the plurality address bits when decoded by the address decoder identify one of the plurality of row decoder-drivers to provide an output, each of the plurality of row decoder-drivers having an input transistor having a gate, the input transistor having a conduction path coupled between a power supply node and the address decoder; and a signal generating circuit, the signal generating circuit for receiving a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit, the signal generating circuit providing an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits, the output maintains the gate of each input transistor near the edge of conduction of said input transistor.
Claim 3
Dependent Claim
26 words
An integrated circuit as recited in claim 1, wherein the edge of conduction is one voltage threshold drop below the voltage at the power supply node.
Claim 4
Dependent Claim
19 words
An integrated circuit as recited in claim 1, wherein the plurality of address bits is comprised of three bits.
Claim 5
Dependent Claim
21 words
An integrated circuit as recited in claim 1 wherein the at least one address decoding transistor is comprised of three transistors.