US5535341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation
Assignee: Intel Corp
•
Filing: 1994-02-24
•
Granted: 1996-07-09
•
Expires: 2014-02-24
Abstract
Abstract A bridge circuit adapted to be associated with first and second bus circuits which bridge circuit includes a first path including a plurality of buffers for storing data or addresses being transferred from the second bus to the first bus, a circuit arrangement for detecting that an interrupt of a presenting-running operation has occurred, a circuit arrangement for determining the state of the plurality of buffers when an interrupt occurs, and apparatus for flushing only those buffers of the plurality which were storing data for transfer when the interrupt occurred.
Inventors
- 👤 Nilesh Shah
- 👤 Rajeev Prasad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:23
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
119 words
A bridge circuit adapted to be associated with first and second bus circuits, the bridge circuit comprising: a path including a plurality of buffers for storing information being transferred between the second bus and the first bus, each of the buffers storing information in a plurality of separately transferable increments, circuitry for flushing the buffers to write the information to its addressed destination, a circuit arrangement for detecting that an interrupt of a presently-running operation has occurred, a circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs, and a circuit arrangement for flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
Claim 2
Dependent Claim
119 words
A bridge circuit adapted to be associated with first and second bus circuits, the bridge circuit comprising: a path including a plurality of buffers for storing information being transferred between the second bus and the first bus, each of the buffers storing information in a plurality of separately transferable increments, circuitry for flushing the buffers to write the information to its addressed destination, a circuit arrangement for detecting that an interrupt of a presently-running operation has occurred, a circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs, and a circuit arrangement for flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
Claim 3
Dependent Claim
39 words
A bridge circuit as claimed in claim 1 in which the circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each buffer.
Claim 4
Dependent Claim
53 words
A bridge circuit as claimed in claim 1 in which the circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each portion of one of the plurality of buffers which may store individual increments of information.
Claim 5
Dependent Claim
70 words
A bridge circuit as claimed in claim 1 in which the circuit arrangement for flushing only those buffers which had stored information for transfer when the interrupt occurred comprises a state machine operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush a portion of each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 6
Dependent Claim
67 words
A bridge circuit as claimed in claim 1 in which the circuit arrangement for flushing only those buffers which had stored information for transfer when the interrupt occurred comprises a state machine operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 7
Dependent Claim
22 words
The bridge circuit of claim 1 further comprising a circuit for directly coupling the first bus circuit to the second bus circuit.
Claim 8
Dependent Claim
130 words
A computer system comprising: a central processor; main memory; a first bus associated with the central processor and main memory; a second bus; and a bridge circuit adapted to transfer information between the first and second buses, the bridge circuit comprising a path including a plurality of buffers for storing information being transferred between the second bus and the first bus, circuitry for flushing the buffers to write the information to its addressed destination, a circuit arrangement for detecting that an interrupt of a presently-running operation has occurred, a circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs, and a circuit arrangement for flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
Claim 9
Dependent Claim
130 words
A computer system comprising: a central processor; main memory; a first bus associated with the central processor and main memory; a second bus; and a bridge circuit adapted to transfer information between the first and second buses, the bridge circuit comprising a path including a plurality of buffers for storing information being transferred between the second bus and the first bus, circuitry for flushing the buffers to write the information to its addressed destination, a circuit arrangement for detecting that an interrupt of a presently-running operation has occurred, a circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs, and a circuit arrangement for flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
Claim 10
Dependent Claim
39 words
A computer system as claimed in claim 7 in which the circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each buffer.
Claim 11
Dependent Claim
53 words
A computer system as claimed in claim 7 in which the circuit arrangement for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each portion of one of the plurality of buffers which may store individual increments of information.
Claim 12
Dependent Claim
67 words
A computer system as claimed in claim 7 in which the circuit arrangement for flushing only those buffers which had stored information for transfer when the interrupt occurred comprises a state machine operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 13
Dependent Claim
70 words
A computer system as claimed in claim 7 in which the circuit arrangement for flushing only those buffers which had stored information for transfer when the interrupt occurred comprises a state machine operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush a portion of each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 14
Dependent Claim
24 words
The computer system of claim 7 wherein said bridge circuit further includes a circuit for directly coupling the first bus to the second bus.
Claim 15
Dependent Claim
129 words
A computer system comprising: processor means; main memory means; first busing means associated with the processor means and main memory means; second busing means; and means for transferring information between the first and second busing means, the means for transferring comprising a path including a plurality of buffering means for storing information being transferred between the second bus and the first bus, means for flushing the buffer means to write the information to its addressed destination, means for detecting that an interrupt of a presently-running operation has occurred, means for determining the state of each of the plurality of buffering means when an interrupt occurs, and means for flushing only those buffering means of the plurality of buffering means which had stored information for transfer when the interrupt occurred.
Claim 16
Dependent Claim
129 words
A computer system comprising: processor means; main memory means; first busing means associated with the processor means and main memory means; second busing means; and means for transferring information between the first and second busing means, the means for transferring comprising a path including a plurality of buffering means for storing information being transferred between the second bus and the first bus, means for flushing the buffer means to write the information to its addressed destination, means for detecting that an interrupt of a presently-running operation has occurred, means for determining the state of each of the plurality of buffering means when an interrupt occurs, and means for flushing only those buffering means of the plurality of buffering means which had stored information for transfer when the interrupt occurred.
Claim 17
Dependent Claim
38 words
A computer system as claimed in claim 13 in which the means for determining the state of each of the plurality of buffers when an interrupt occurs comprises state machine means for registering the condition of each buffer.
Claim 18
Dependent Claim
52 words
A computer system as claimed in claim 13 in which the means for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each portion of one of the plurality of buffers which may store individual increments of information.
Claim 19
Dependent Claim
67 words
A computer system as claimed in claim 13 in which the means for flushing only those buffering means which had stored information for transfer when the interrupt occurred comprises state machine means operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 20
Dependent Claim
70 words
A computer system as claimed in claim 13 in which the means for flushing only those buffering means which had stored information for transfer when the interrupt occurred comprises state machine means operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush a portion of each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 21
Dependent Claim
131 words
A bridge circuit adapted to be associated with first and second busing means, the bridge circuit comprising: means for transferring information between the first and second busing means, including a path including a plurality of buffering means for storing information being transferred between the second bus and the first bus, each of the buffering means storing information in a plurality of separately transferable increments, means for flushing the buffer means to write the information to its addressed destination, means for detecting that an interrupt of a presently-running operation has occurred, means for determining the state of each of the plurality of buffering means when an interrupt occurs, and means for flushing only those buffering means of the plurality of buffering means which had stored information for transfer when the interrupt occurred.
Claim 22
Dependent Claim
131 words
A bridge circuit adapted to be associated with first and second busing means, the bridge circuit comprising: means for transferring information between the first and second busing means, including a path including a plurality of buffering means for storing information being transferred between the second bus and the first bus, each of the buffering means storing information in a plurality of separately transferable increments, means for flushing the buffer means to write the information to its addressed destination, means for detecting that an interrupt of a presently-running operation has occurred, means for determining the state of each of the plurality of buffering means when an interrupt occurs, and means for flushing only those buffering means of the plurality of buffering means which had stored information for transfer when the interrupt occurred.
Claim 23
Dependent Claim
38 words
A computer system as claimed in claim 18 in which the means for determining the state of each of the plurality of buffers when an interrupt occurs comprises state machine means for registering the condition of each buffer.
Claim 24
Dependent Claim
52 words
A computer system as claimed in claim 18 in which the means for determining the state of each of the plurality of buffers when an interrupt occurs comprises a state machine for registering the condition of each portion of one of the plurality of buffers which may store individual increments of information.
Claim 25
Dependent Claim
67 words
A computer system as claimed in claim 18 in which the means for flushing only those buffering means which had stored information for transfer when the interrupt occurred comprises state machine means operating in response to the determination of the state of each buffer when the interrupt occurs, the state machine operating to flush each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 26
Dependent Claim
70 words
A computer system as claimed in claim 18 in which the means for flushing only those buffering means which had stored information for transfer when the interrupt occurred comprises state machine means operating in response to a determination of the state of each buffer when an interrupt occurs, the state machine operating to flush a portion of each buffer which had stored valid data for transfer when the interrupt occurred.
Claim 27
Independent Claim
69 words
A method of flushing a plurality of data buffers used to transfer information between a first bus and a second bus in a computer system comprising the steps of: detecting that an interrupt of a presenting-running operation has occurred, determining the state of the buffers when the interrupt occurs, and flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
Claim 28
Independent Claim
69 words
A method of flushing a plurality of data buffers used to transfer information between a first bus and a second bus in a computer system comprising the steps of: detecting that an interrupt of a presenting-running operation has occurred, determining the state of the buffers when the interrupt occurs, and flushing only those buffers of the plurality of buffers which had stored information for transfer when the interrupt occurred.
References Cited (Backward Citations)
US5117486A
Cited
US5179706A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |