US5541883A
Expired / Lapsed
US
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Method and apparatus for simultaneous long writes of multiple cells of a row in a static ram
Assignee: Renesas Electronics America Inc
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Filing: 1995-05-09
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Granted: 1996-07-30
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Expires: 2015-05-09
Abstract
Abstract A multiple column select circuit enables simultaneous selection of multiple columns of a static RAM to allow a "long write" test for leakage defects whereas a fewer number of columns are selected during normal operation of the static RAM. In one embodiment, a multiple column select circuit includes an inverter, the output lead of which is coupled to the pull-up circuits of each respective column of the static RAM. When a multiple column select input signal is asserted, a supply voltage supplied to each of the pull-up circuits by the output lead of the inverter switches from V DD to ground potential thereby simultaneously selecting multiple columns of the static RAM. In another embodiment, a multiple column select circuit drives each individual column select line of the memory. When a multiple column select input signal is asserted, each individual column select line is asserted, thereby selecting all columns. When the multiple column select input signal is not asserted, a column addressing circuit controls the voltages on the column select lines through the multiple column select circuit to select only one column.
Inventors
- 👤 William L. Devanney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:55
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
248 words
An integrated circuit, comprising: a plurality of static random access memory cells organized in a matrix having a plurality of rows and a plurality of columns, each of said cells having a bit output node and a bit transmission gate; a plurality of bit lines, said bit lines having a one-to-one correspondence with said columns of memory cells, one terminal of the bit transmission gate of each memory cell being coupled to the bit output node of said memory cell, another terminal of the bit transmission gate of said memory cell being coupled to a bit line corresponding with the column within which said memory cell is disposed; means for testing said plurality of memory cells by driving a first digital logic voltage onto a first number of said bit lines for a first period of time in a first write cycle when the transmission gates coupled to said first number of said bit lines are controlled to be nonconductive and when the memory cells of which said transmission gates are part store a second digital logic voltage on their respective bit output nodes; and means for writing data into memory cells by driving a data voltage onto a second number of said bit lines for a second period of time in a second write cycle, said first number of bit lines being greater than said second number of bit lines, said first period of time being of a significantly longer duration than said second period of time.
Claim 2
Dependent Claim
248 words
An integrated circuit, comprising: a plurality of static random access memory cells organized in a matrix having a plurality of rows and a plurality of columns, each of said cells having a bit output node and a bit transmission gate; a plurality of bit lines, said bit lines having a one-to-one correspondence with said columns of memory cells, one terminal of the bit transmission gate of each memory cell being coupled to the bit output node of said memory cell, another terminal of the bit transmission gate of said memory cell being coupled to a bit line corresponding with the column within which said memory cell is disposed; means for testing said plurality of memory cells by driving a first digital logic voltage onto a first number of said bit lines for a first period of time in a first write cycle when the transmission gates coupled to said first number of said bit lines are controlled to be nonconductive and when the memory cells of which said transmission gates are part store a second digital logic voltage on their respective bit output nodes; and means for writing data into memory cells by driving a data voltage onto a second number of said bit lines for a second period of time in a second write cycle, said first number of bit lines being greater than said second number of bit lines, said first period of time being of a significantly longer duration than said second period of time.
Claim 3
Dependent Claim
12 words
The integrated circuit of claim 1, wherein said second number is one.
Claim 4
Dependent Claim
14 words
The integrated circuit of claim 1, wherein said second number is greater than one.
Claim 5
Dependent Claim
31 words
The integrated circuit of claim 2, further comprising a second plurality of bit lines, said second plurality of bit lines also having a one-to-one correspondence with said columns of memory cells.
Claim 6
Dependent Claim
42 words
The integrated circuit of claim 1, wherein said means for testing comprises: a multiple column select lead coupled to a plurality of column pull-up circuits; and a digital logic element driving said first digital logic voltage onto said multiple column select lead.
Claim 7
Dependent Claim
44 words
The integrated circuit of claim 1, wherein said means for testing comprises: a plurality of digital logic elements and a multiple column select input lead, an input terminal of each of said digital logic elements being coupled to said multiple column select input lead.
Claim 8
Independent Claim
196 words
A method, comprising: (a) driving a test voltage onto a first number of bit lines of a static random access memory integrated circuit for a first period of time in a first write cycle, a plurality of memory cells being coupled to said first number of bit lines, each of said memory cells having a bit output node and a bit transmission gate, one terminal of each said bit column transmission gate being coupled to a corresponding one of said first number of bit lines, another terminal of each said bit column transmission gate being coupled to the bit output node of the memory cell of which the transmission gate is a part, all the bit column transmission gates coupled to said first number of bit lines being controlled to be nonconductive; and (b) driving a data voltage onto a second number of bit lines of said static random access memory integrated circuit for a second period of time in a second write cycle, said first number of bit lines being greater than said second number of bit lines, said first period of time being of a significantly longer duration than said second period of time.
Claim 9
Independent Claim
196 words
A method, comprising: (a) driving a test voltage onto a first number of bit lines of a static random access memory integrated circuit for a first period of time in a first write cycle, a plurality of memory cells being coupled to said first number of bit lines, each of said memory cells having a bit output node and a bit transmission gate, one terminal of each said bit column transmission gate being coupled to a corresponding one of said first number of bit lines, another terminal of each said bit column transmission gate being coupled to the bit output node of the memory cell of which the transmission gate is a part, all the bit column transmission gates coupled to said first number of bit lines being controlled to be nonconductive; and (b) driving a data voltage onto a second number of bit lines of said static random access memory integrated circuit for a second period of time in a second write cycle, said first number of bit lines being greater than said second number of bit lines, said first period of time being of a significantly longer duration than said second period of time.
Claim 10
Dependent Claim
38 words
The method of claim 7, wherein step (a) is used to test the static random access memory integrated circuit for defects, and wherein step (b) is an ordinary write cycle of the static random access memory integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |