US5546402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash-erase-type nonvolatile semiconductor storage device
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1996-08-13
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Expires: 2015-06-07
Abstract
Abstract An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.
Inventors
- 👤 Hideto Niijima
- 👤 Takashi Toyooka
- 👤 Akashi Satoh
- 👤 Yoshinori Sakaue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/22; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
212 words
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first set and a second set such that particular contents of data stored in the memory cells of said second set are maintained when data stored in the memory cells of said first set are erased en block by applying an electric field between the word line and the memory cells of the first set as a single voltage charge pulse to the memory cells of the first set, the memory cells of said first set are logically grouped into a plurality of blocks each consisting of a plurality of memory cells, those blocks include regular blocks that are usually employed for the storage of data and redundant blocks that are employed for block replacement, and the memory cells of said second set are employed to store data used for identifying defective regular blocks and redundant blocks that are employed as replacements thereof, and said second set is also employed to store error correction codes (ECCs) generated for said data used for identifying said defective blocks and said redundant blocks.
Claim 2
Dependent Claim
212 words
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first set and a second set such that particular contents of data stored in the memory cells of said second set are maintained when data stored in the memory cells of said first set are erased en block by applying an electric field between the word line and the memory cells of the first set as a single voltage charge pulse to the memory cells of the first set, the memory cells of said first set are logically grouped into a plurality of blocks each consisting of a plurality of memory cells, those blocks include regular blocks that are usually employed for the storage of data and redundant blocks that are employed for block replacement, and the memory cells of said second set are employed to store data used for identifying defective regular blocks and redundant blocks that are employed as replacements thereof, and said second set is also employed to store error correction codes (ECCs) generated for said data used for identifying said defective blocks and said redundant blocks.
Claim 3
Dependent Claim
31 words
The semiconductor storage device of claim 1, wherein the memory cells of said second set are employed to store data indicating the unavailability of the memory cells of said first set.
Claim 4
Dependent Claim
241 words
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first set and a second set such that particular contents of data stored in the memory cells of said second set are maintained when data stored in the memory cells of said first set are erased en block by applying an electric field between the word line and the memory cells of the first set as a single voltage charge pulse to the memory cells of the first set, the memory cells of said first set are logically grouped into a plurality of blocks each consisting of a plurality of memory cells, those blocks include regular blocks that are usually employed for the storage of data and redundant blocks that are employed for blocks replacement, and the memory cells of said second set are employed to store data used for identifying defective regular blocks and redundant blocks that are employed as replacements thereof, and the memory cells of said second set are also employed to store error correction codes (ECCs) generated for said data used for identifying said defective blocks and said redundant blocks, and the memory cells of said second set are further employed to store data indicating the unavailability of the memory cells of said first set.
Claim 5
Dependent Claim
241 words
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first set and a second set such that particular contents of data stored in the memory cells of said second set are maintained when data stored in the memory cells of said first set are erased en block by applying an electric field between the word line and the memory cells of the first set as a single voltage charge pulse to the memory cells of the first set, the memory cells of said first set are logically grouped into a plurality of blocks each consisting of a plurality of memory cells, those blocks include regular blocks that are usually employed for the storage of data and redundant blocks that are employed for blocks replacement, and the memory cells of said second set are employed to store data used for identifying defective regular blocks and redundant blocks that are employed as replacements thereof, and the memory cells of said second set are also employed to store error correction codes (ECCs) generated for said data used for identifying said defective blocks and said redundant blocks, and the memory cells of said second set are further employed to store data indicating the unavailability of the memory cells of said first set.
References Cited (Backward Citations)
US4698787A
Cited
JPS63268194A
Cited
US4949309A
Cited
US5268870A
Cited
JPH02292798A
Cited
US5297148A
Cited
US5200959A
Cited
US5185718A
Cited
US5392253A
Cited
US5270980A
Cited
US5278793A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |