← Back to Patent Explorer
US5548099A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making an electronics module having air bridge protection without large area ablation

Assignee: Lockheed Martin Corp
•
Filing: 1994-09-13
•
Granted: 1996-08-20
•
Expires: 2014-09-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a method for preserving an air bridge structure on an integrated circuit chip, without sacrificing metallization routing area in an overlying high density interconnect structure, a protective layer is sublimed over the air bridge to provide mechanical strength while preventing contamination and deformation during processing. A high density interconnect structure is applied over the chip and protective layer. A small portion of the high density interconnect structure is removed from the area over the air bridge structure, and the protective layer is then sublimed away, leaving the resultant structure with an undamaged air bridge which is free of residue.

Inventors

  • 👤 Herbert S. Cole, Jr.
  • 👤 Theresa A. Sitnik-Nieters

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 01:18
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W44/00; H10W44/20; H10W70/00; H10W70/60; H10W70/611; H10W70/614; H10W74/10; H10W74/111; H10W74/124; H10W70/099; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/851; H10W72/874; H10W90/00; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 202 words
A method for making an electronics module, comprising the steps of: (1) disposing a plurality of electronic chips on a substrate surface, at least some of the chips including contact pads, and at least one of the chips including a sensitive structure; (2) encapsulating the sensitive structure with a sublimable protective layer thereby creating an encapsulating volume, the sublimable protective layer supporting the sensitive structure from all sides, and inhibiting the sensitive structure from processing contamination; (3) applying at least one multilayer of a high density interconnect structure, comprising the steps of: (a) applying a dielectric film layer over the chips and the substrate surface; (b) providing a plurality of via openings in the dielectric film layer, the openings being disposed over at least some of the contact pads; and (c) providing a pattern of electrical conductors on the film layer so that the conductors extend between the via openings so as to electrically connect selected contact pads; (4) removing a portion of the multilayer of high density interconnect structure to provide a channel extending from the encapsulating volume through the high density interconnect structure to an exterior surface; and (5) removing the protective layer from the encapsulating volume through the channel.
Claim 2
Independent Claim 202 words
A method for making an electronics module, comprising the steps of: (1) disposing a plurality of electronic chips on a substrate surface, at least some of the chips including contact pads, and at least one of the chips including a sensitive structure; (2) encapsulating the sensitive structure with a sublimable protective layer thereby creating an encapsulating volume, the sublimable protective layer supporting the sensitive structure from all sides, and inhibiting the sensitive structure from processing contamination; (3) applying at least one multilayer of a high density interconnect structure, comprising the steps of: (a) applying a dielectric film layer over the chips and the substrate surface; (b) providing a plurality of via openings in the dielectric film layer, the openings being disposed over at least some of the contact pads; and (c) providing a pattern of electrical conductors on the film layer so that the conductors extend between the via openings so as to electrically connect selected contact pads; (4) removing a portion of the multilayer of high density interconnect structure to provide a channel extending from the encapsulating volume through the high density interconnect structure to an exterior surface; and (5) removing the protective layer from the encapsulating volume through the channel.
Claim 3
Dependent Claim 27 words
The method for making an electronics module according to claim 1, wherein the method is carried out at a temperature between about 240° C. and 260° C.
Claim 4
Dependent Claim 22 words
The method for making an electronics module according to claim 1, wherein the channel is orthogonal with respect to the substrate surface.
Claim 5
Dependent Claim 19 words
The method for making an electronics module according to claim 1, wherein the protective layer is an organic monomer.
Claim 6
Dependent Claim 28 words
The method for making an electronics module according to claim 4, wherein the protective layer is selected from the group consisting essentially of perylene, anthraquinone, quinalizarin and alizarin.
Claim 7
Dependent Claim 35 words
The method for making an electronics module according to claim 5, wherein the protective layer has a vapor pressure of greater to or equal than about 10 torr, at a temperature of about 170° C.
Claim 8
Dependent Claim 35 words
The method of claim 1, wherein the step of removing the multilayer of high density interconnect structure to provide the channel comprises laser ablating the dielectric film layer in the area over the encapsulating volume.
Claim 9
Dependent Claim 30 words
The method of claim 1, wherein the step of removing the protective layer comprises heating the module to a temperature and pulling a vacuum sufficient to sublime the protective layer.
Claim 10
Dependent Claim 13 words
The method of claim 1, wherein the sensitive structure is an air bridge.
Claim 11
Dependent Claim 21 words
The method of claim 1, wherein the step of removing the protective layer leaves the sensitive structure essentially free of contamination.
Claim 12
Dependent Claim 14 words
The method of claim 1, wherein the encapsulating volume is substantially devoid of material.

References Cited (Backward Citations)

US4783695A Cited
US4933042A Cited
US4835704A Cited
US4878991A Cited
US4894115A Cited
US5331203A Cited
US5161093A Cited
US5338975A Cited
US5422513A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-08-20 2000-02-19 2000-08-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-08-20 2004-02-19 2004-08-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-08-20 2008-02-19 2008-08-20 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag