US5553268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory operations priority scheme for microprocessors
Assignee: Renesas Electronics America Inc
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Filing: 1991-06-14
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Granted: 1996-09-03
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Expires: 2011-06-14
Abstract
Abstract A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a "direct memory access" (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.
Inventors
- 👤 Avigdor Willenz
- 👤 Philip Bourekas
- 👤 Yehayahu Mor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
82 words
A structure for granting use of a memory bus in a computer system, comprising: means for receiving an instruction read request; means for receiving a data read request; means for receiving a write request; means for receiving a clock signal; means for granting use of said memory bus at a transition of said clock signal accord; to the decreasing priority order; (i) any said instruction read request received; (ii) any said write request received; and (iii) any said data read request received.
Claim 2
Dependent Claim
82 words
A structure for granting use of a memory bus in a computer system, comprising: means for receiving an instruction read request; means for receiving a data read request; means for receiving a write request; means for receiving a clock signal; means for granting use of said memory bus at a transition of said clock signal accord; to the decreasing priority order; (i) any said instruction read request received; (ii) any said write request received; and (iii) any said data read request received.
Claim 3
Dependent Claim
34 words
A structure as in claim 1, further comprising means for receiving a DMA request, and wherein said granting means provides any said DMA request a higher priority over any said instruction read request received.
Claim 4
Dependent Claim
31 words
A structure as in claim 1, wherein said computer system comprises a cache memory, and said instruction and data read requests includes reading requests arising from misses in said cache memory.
Claim 5
Dependent Claim
17 words
A structure as in claim 1, wherein said computer system comprises a microprocessor with an on-chip cache.
Claim 6
Dependent Claim
23 words
A structure as in claim 1, wherein said granting means grants use of said memory bus only when said memory bus is free.
Claim 7
Independent Claim
87 words
A method for granting use of a memory bus in a computer system, comprising the steps of: providing means for receiving an instruction read request; providing means for receiving a data read request; providing means for receiving a write request; providing means for receiving a clock signal; granting use of said memory bus at a transition of said clock signal according to the decreasing priority order: (i) any said instruction read request received; ii) any said write request received; and (iii) any said data read request received.
Claim 8
Independent Claim
87 words
A method for granting use of a memory bus in a computer system, comprising the steps of: providing means for receiving an instruction read request; providing means for receiving a data read request; providing means for receiving a write request; providing means for receiving a clock signal; granting use of said memory bus at a transition of said clock signal according to the decreasing priority order: (i) any said instruction read request received; ii) any said write request received; and (iii) any said data read request received.
Claim 9
Dependent Claim
43 words
A method as in claim 6, further comprising the step of providing means for receiving a DMA request, and wherein said granting step comprises the step of according any said DMA request received a higher priority over any said instruction read request received.
Claim 10
Dependent Claim
48 words
A method as in claim 6, wherein said computer system comprises a cache memory, and said steps of providing means for receiving instruction and data read requests include respectively the steps of providing means for receiving instruction and data reading requests arising from misses in said cache memory.
Claim 11
Dependent Claim
17 words
A method as in claim 6, wherein said computer system comprises a microprocessor with an on-chip cache.
Claim 12
Dependent Claim
23 words
A method as in claim 6, wherein said granting step grants use of said memory bus only when said memory bus is free.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |