US5557568A
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US
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Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
Assignee: Toshiba Corp
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Filing: 1995-04-24
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Granted: 1996-09-17
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Expires: 2015-04-24
Abstract
Abstract A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
Inventors
- 👤 Junichi Miyamoto
- 👤 Yasuo Itoh
- 👤 Yoshihisa Iwata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/10; G11C16/24; G11C7/00; G11C7/02; G11C7/10; G11C7/1006; G11C7/1048
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
300 words
A method of operating a non-volatile semiconductor memory device which includes a non-volatile memory cell, a bit line and a word line connected to said non-volatile memory cell, a flip-flop circuit settable in one of a first and a second state, a data setting circuit responsive to a potential of said bit line for setting said flip-flop circuit in the second state, and a data resetting circuit for resetting said flip-flop circuit in a reset state, the method comprising: a first step of writing data to said non-volatile memory cell during a write operation, wherein said flip-flop circuit is set in one of the first and second states, said word line and said bit line are driven to select said non-volatile memory cell for writing, and write data, corresponding to the state of said flip-flop circuit, is transmitted to said bit line for supplying the write data to said non-volatile memory cell; a second step of verifying the writing of the write data to said non-volatile memory cell during a verify operation, wherein, when said flip-flop circuit is set in the first state and when a MOS transistor of said data setting circuit having a gate supplied with a potential of said bit line is turned on, the state of said flip-flop circuit is forcibly inverted from the first state to the second state; and a third step of reading out data from said non-volatile memory cell during a read-out operation, wherein said flip-flop circuit is reset in the reset state by said data resetting circuit, said word line and said bit line are driven to select said non-volatile memory cell for reading, readout data corresponding to data stored in said non-volatile memory cell is transmitted to said bit line, and the readout data is set in said flip-flop circuit.
Claim 2
Independent Claim
300 words
A method of operating a non-volatile semiconductor memory device which includes a non-volatile memory cell, a bit line and a word line connected to said non-volatile memory cell, a flip-flop circuit settable in one of a first and a second state, a data setting circuit responsive to a potential of said bit line for setting said flip-flop circuit in the second state, and a data resetting circuit for resetting said flip-flop circuit in a reset state, the method comprising: a first step of writing data to said non-volatile memory cell during a write operation, wherein said flip-flop circuit is set in one of the first and second states, said word line and said bit line are driven to select said non-volatile memory cell for writing, and write data, corresponding to the state of said flip-flop circuit, is transmitted to said bit line for supplying the write data to said non-volatile memory cell; a second step of verifying the writing of the write data to said non-volatile memory cell during a verify operation, wherein, when said flip-flop circuit is set in the first state and when a MOS transistor of said data setting circuit having a gate supplied with a potential of said bit line is turned on, the state of said flip-flop circuit is forcibly inverted from the first state to the second state; and a third step of reading out data from said non-volatile memory cell during a read-out operation, wherein said flip-flop circuit is reset in the reset state by said data resetting circuit, said word line and said bit line are driven to select said non-volatile memory cell for reading, readout data corresponding to data stored in said non-volatile memory cell is transmitted to said bit line, and the readout data is set in said flip-flop circuit.
Claim 3
Dependent Claim
46 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein, in the first step, data for setting said flip-flop circuit in one of the first and second states is supplied from an input/output line to said flip-flop circuit via a column gate.
Claim 4
Dependent Claim
42 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein, in the third step, the resetting of said flip-flop circuit is effected by supplying reset data to said flip-flop circuit from an input/output line via a column gate.
Claim 5
Dependent Claim
42 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein, in the third step, the resetting of said flip-flop circuit is effected by switching on a reset switch element of said resetting circuit which receives a reset signal.
Claim 6
Dependent Claim
47 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein, in the first step, the write data is supplied to said non-volatile memory cell while the write data corresponding to the state of said flip-flop circuit is being transmitted to said bit line.
Claim 7
Dependent Claim
38 words
The method of operating a non-volatile semiconductor memory device according to claim 5, wherein data for setting said flip-flop circuit in one of the first and second states is supplied from an input/output line via a column gate.
Claim 8
Dependent Claim
25 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein said bit line is precharged prior to obtaining the readout data.
Claim 9
Dependent Claim
30 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein the readout data is output to the outside from a column gate via an input/output line.
Claim 10
Dependent Claim
44 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein a signal indicating normal completion of the verify operation is generated when said flip-flop circuit is set in the second state within a predetermined time period during the verify operation.
Claim 11
Dependent Claim
31 words
The method of operating a non-volatile semiconductor memory device according to claim 1, wherein a time period is provided in which the second step can be performed two or more times.
Claim 12
Independent Claim
308 words
A method of operating a non-volatile semiconductor memory device which includes non-volatile memory cells, word lines and bit lines connected to said non-volatile memory cells, flip-flop circuits each settable in one of a first state and a second state, data setting circuits each responsive to a potential of one of said bit lines for setting a respective corresponding one of said flip-flop circuits in the second state, and data resetting circuits each for resetting a respective corresponding one of said flip-flop circuits in a reset state, the method comprising: a first step of writing data to said non-volatile memory cells during a write operation, wherein each of said flip-flop circuits is set in one of the first and second states, and write data, corresponding to the states of said flip-flop circuits, is transmitted to said bit lines for supplying the write data to non-volatile memory cells selected by driving said word lines and bit lines; a second step of verifying the writing of the write data to said non-volatile memory cells during a verify operation, wherein, when ones of said flip-flop circuits are set in the first state and when MOS transistors of data setting circuits having gates supplied with potentials of said bit lines are turned on, the state of said ones of said flip-flop circuits is forcibly inverted from the first state to the second state to thereby uniformly set all of said flip-flop circuits in the second state; and a third step of reading out data from said non-volatile memory cells during a read-out operation, wherein said flip-flop circuits are reset in the reset state by said data resetting circuits, readout data corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits.
Claim 13
Independent Claim
308 words
A method of operating a non-volatile semiconductor memory device which includes non-volatile memory cells, word lines and bit lines connected to said non-volatile memory cells, flip-flop circuits each settable in one of a first state and a second state, data setting circuits each responsive to a potential of one of said bit lines for setting a respective corresponding one of said flip-flop circuits in the second state, and data resetting circuits each for resetting a respective corresponding one of said flip-flop circuits in a reset state, the method comprising: a first step of writing data to said non-volatile memory cells during a write operation, wherein each of said flip-flop circuits is set in one of the first and second states, and write data, corresponding to the states of said flip-flop circuits, is transmitted to said bit lines for supplying the write data to non-volatile memory cells selected by driving said word lines and bit lines; a second step of verifying the writing of the write data to said non-volatile memory cells during a verify operation, wherein, when ones of said flip-flop circuits are set in the first state and when MOS transistors of data setting circuits having gates supplied with potentials of said bit lines are turned on, the state of said ones of said flip-flop circuits is forcibly inverted from the first state to the second state to thereby uniformly set all of said flip-flop circuits in the second state; and a third step of reading out data from said non-volatile memory cells during a read-out operation, wherein said flip-flop circuits are reset in the reset state by said data resetting circuits, readout data corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits.
Claim 14
Dependent Claim
48 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein, in the first step, data for setting each of said flip-flop circuits in one of the first and second states is supplied from an input/output line to said flip-flop circuits via associated column gates.
Claim 15
Dependent Claim
42 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein, in the third step, the resetting of said flip-flop circuits is effected by supplying reset data to said flip-flop circuits from an input/output line via associated column gates.
Claim 16
Dependent Claim
41 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein, in the third step, the resetting of said flip-flop circuits is effected by turning on reset switch elements of said resetting circuits which receive a reset signal.
Claim 17
Dependent Claim
47 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein, in the first step, the write data is supplied to said selected memory cells while the write data corresponding to the states of said flip-flop circuits is being transmitted to said bit lines.
Claim 18
Dependent Claim
38 words
The method of operating a non-volatile semiconductor memory device according to claim 15, wherein data for setting said flip-flop circuits in one of the first and second states is supplied from an input/output line via associated column gates.
Claim 19
Dependent Claim
25 words
The method of using a non-volatile semiconductor memory device according to claim 11, wherein said bit lines are precharged prior to obtaining the readout data.
Claim 20
Dependent Claim
29 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein the readout data is output to the outside from column gates via an input/output line.
Claim 21
Dependent Claim
46 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein a signal indicating normal completion of the verify operation is generated when all of said flip-flop circuits are set in the second state within a predetermined time period during the verify operation.
Claim 22
Dependent Claim
31 words
The method of operating a non-volatile semiconductor memory device according to claim 11, wherein a time period is provided in which the second step can be performed two or more times.
Claim 23
Independent Claim
313 words
A method of operating a non-volatile semiconductor memory device which includes non-volatile memory cells, bit lines and word lines connected to said non-volatile memory cells, flip-flop circuits each settable in one of a first state and a second state, data setting circuits each responsive to a potential of one of said bit lines for setting a respective corresponding one of said flip-flop circuits in the second state, and data resetting circuits each for resetting a respective corresponding one of said flip-flop circuits in the reset state, the method comprising: a first step wherein, in a write operation, said flip-flop circuits are each set in one of the first and second states, write data, corresponding to the states of said flip-flop circuits, is transmitted from said flip-flop circuits to said bit lines, and data corresponding to the write data is supplied to non-volatile memory cells selected by driving said word lines and said bit lines; a second step wherein, in a readout operation, said flip-flop circuits are reset by said data resetting circuits, readout data corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits; and a third step wherein, in a verify operation, said bit lines are precharged, and, after the lapse of a transition time of potentials of said bit lines corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines, if one or more of said flip-flop circuits is set in the first state, the states of these one or more flip-flop circuits are forcibly inverted to the second state by MOS transistors of said data setting circuits which are turned on in accordance with the potentials of said bit lines, thereby uniformly setting said flip-flop circuits in the second state.
Claim 24
Independent Claim
313 words
A method of operating a non-volatile semiconductor memory device which includes non-volatile memory cells, bit lines and word lines connected to said non-volatile memory cells, flip-flop circuits each settable in one of a first state and a second state, data setting circuits each responsive to a potential of one of said bit lines for setting a respective corresponding one of said flip-flop circuits in the second state, and data resetting circuits each for resetting a respective corresponding one of said flip-flop circuits in the reset state, the method comprising: a first step wherein, in a write operation, said flip-flop circuits are each set in one of the first and second states, write data, corresponding to the states of said flip-flop circuits, is transmitted from said flip-flop circuits to said bit lines, and data corresponding to the write data is supplied to non-volatile memory cells selected by driving said word lines and said bit lines; a second step wherein, in a readout operation, said flip-flop circuits are reset by said data resetting circuits, readout data corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits; and a third step wherein, in a verify operation, said bit lines are precharged, and, after the lapse of a transition time of potentials of said bit lines corresponding to data stored in non-volatile memory cells selected by driving said word lines and bit lines, if one or more of said flip-flop circuits is set in the first state, the states of these one or more flip-flop circuits are forcibly inverted to the second state by MOS transistors of said data setting circuits which are turned on in accordance with the potentials of said bit lines, thereby uniformly setting said flip-flop circuits in the second state.
Claim 25
Dependent Claim
43 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein in the write operation, there is a time period at an initial state in which data in all of said non-volatile memory cells is set in an erase state.
Claim 26
Dependent Claim
46 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein, in the write operation, data for setting said flip-flop circuits in one of the first and second states is supplied to said flip-flop circuits via associated column gates from an input/output line.
Claim 27
Dependent Claim
42 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein the resetting of said flip-flop circuits in the readout operation is effected by supplying reset data to said flip-flop circuits via associated column gates from an input/output line.
Claim 28
Dependent Claim
41 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein the resetting of said flip-flop circuits in said readout operation is effected by switching on reset MOS transistors of said resetting circuits which receive a reset signal.
Claim 29
Dependent Claim
133 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein in the readout operation, a precharge time period is provided in which, prior to selection of said non-volatile memory cells by driving said word lines and bit lines, the associated bit lines are precharged in accordance with the resetting of said flip-flop circuits, said bit lines and the associated flip-flop circuits being electrically disconnected from each other during the precharge time period, the readout data corresponding to data stored in non-volatile memory cells selected by driving word lines and said bit lines is subsequently transmitted to said bit lines, and the readout data is set in said flip-flop circuits by MOS transistors of said data setting circuits which are switched on in accordance with potentials of said bit lines.
Claim 30
Dependent Claim
38 words
The method of operating a non-volatile memory device according to claim 21, wherein in the readout operation, the readout data set in said flip-flop circuits is output to the outside from associated column gates via an input/output line.
Claim 31
Dependent Claim
80 words
The method of operating a non-volatile semiconductor memory device according to claim 21, wherein a time period is provided in which the verify operation and the write operation are alternately switched, and in one cycle of the verify operation, when said MOS transistors having gates supplied with potentials of said bit lines are turned off and when at least one flip-flop circuit is set in the first state, the write operation is restarted and then the verify operation is restored.
Claim 32
Dependent Claim
40 words
The method of operating a non-volatile semiconductor memory device according to claim 28, wherein, in the verify operation, a signal indicating normal completion of the verify operation is generated when all said flip-flop circuits are set in the second state.
Claim 33
Independent Claim
385 words
A method of using a non-volatile semiconductor memory device having a verify mode, said memory device comprising: non-volatile memory cells; bit lines connected to said non-volatile memory cells; word lines connected to said non-volatile memory cells; flip-flop circuits which are set in one of a first state and a second state; switching circuits responsive to switching signals for electrically connecting said bit lines and said flip-flop circuits during at least a write operation for writing the respective write data to said non-volatile memory cells; data setting circuits responsive to potentials of said bit lines for setting said flip-flop circuits in respective second states; and data resetting circuits responsive to reset signals for resetting said flip-flop circuits in respective reset states, the method comprising: a first step wherein, in a write mode, said flip-flop circuits are each set in one of a first and a second state, write data corresponding to the states of said flip-flop circuits is transmitted from said flip-flop circuits to said bit lines, and said word lines and bit lines are driven to store data corresponding to the write data in selected memory cells; a second step wherein, in a readout mode, transmission paths between said flip-flop circuits and said bit lines are cut off by said switching circuits, said flip-flop circuits are reset by said resetting circuits, readout data corresponding to data stored in memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits by said data setting circuits while the readout data is being transmitted to said bit lines; and a third step wherein, in a verify mode, the transmission paths of the write data from said flip-flop circuits to said bit lines are cut off by said switching circuits, and, after the lapse of a transition time of potentials of said bit lines corresponding to data stored in memory cells selected by driving said word lines and bit lines, if one or more of said flip-flop circuits is set in the first state, the states of these one or more flip-flop circuits are forcibly inverted to the second state by said data setting circuits in accordance with the potentials said bit lines, thereby uniformly setting said flip-flop circuits in the second state.
Claim 34
Independent Claim
385 words
A method of using a non-volatile semiconductor memory device having a verify mode, said memory device comprising: non-volatile memory cells; bit lines connected to said non-volatile memory cells; word lines connected to said non-volatile memory cells; flip-flop circuits which are set in one of a first state and a second state; switching circuits responsive to switching signals for electrically connecting said bit lines and said flip-flop circuits during at least a write operation for writing the respective write data to said non-volatile memory cells; data setting circuits responsive to potentials of said bit lines for setting said flip-flop circuits in respective second states; and data resetting circuits responsive to reset signals for resetting said flip-flop circuits in respective reset states, the method comprising: a first step wherein, in a write mode, said flip-flop circuits are each set in one of a first and a second state, write data corresponding to the states of said flip-flop circuits is transmitted from said flip-flop circuits to said bit lines, and said word lines and bit lines are driven to store data corresponding to the write data in selected memory cells; a second step wherein, in a readout mode, transmission paths between said flip-flop circuits and said bit lines are cut off by said switching circuits, said flip-flop circuits are reset by said resetting circuits, readout data corresponding to data stored in memory cells selected by driving said word lines and bit lines is transmitted to said bit lines, and the readout data is set in said flip-flop circuits by said data setting circuits while the readout data is being transmitted to said bit lines; and a third step wherein, in a verify mode, the transmission paths of the write data from said flip-flop circuits to said bit lines are cut off by said switching circuits, and, after the lapse of a transition time of potentials of said bit lines corresponding to data stored in memory cells selected by driving said word lines and bit lines, if one or more of said flip-flop circuits is set in the first state, the states of these one or more flip-flop circuits are forcibly inverted to the second state by said data setting circuits in accordance with the potentials said bit lines, thereby uniformly setting said flip-flop circuits in the second state.
Claim 35
Dependent Claim
42 words
The method of using a non-volatile semiconductor memory device according to claim 30, wherein in the write mode, there is a time period at an initial stage in which data in all of said memory cells is set in an erase state.
Claim 36
Dependent Claim
39 words
The method of using a non-volatile semiconductor memory device according to claim 30, wherein, in the write mode, the states of said flip-flop circuits are set in accordance with data supplied thereto via associated column gates from input/output line.
Claim 37
Dependent Claim
34 words
The method of using a non-volatile semiconductor memory device according to claim 30, wherein in the readout mode, the readout data is output to the outside from associated column gates via an input/output line.
Claim 38
Dependent Claim
72 words
The method of using a non-volatile semiconductor memory device according to claim 30, wherein there is a time period in which the verify mode and the write mode are alternately switched, and in one cycle of the verify mode, when said data setting circuits are turned off and when at least one flip-flop circuit is set in the first state, the write mode is restarted and then the verify mode is restored.
Claim 39
Dependent Claim
40 words
The method of using a non-volatile semiconductor memory device according to claim 34, wherein, in the verify mode, a signal indicating normal completion of the verify mode is generated when all said flip-flop circuits are set in the second state.
References Cited (Backward Citations)
US5105384A
Cited
US4958317A
Cited
US4943962A
Cited
US5414658A
Cited
US5293350A
Cited
GB2264578A
Cited
US5299162A
Cited
EP0642133A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |