US5559988A
Expired / Lapsed
US
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Method and circuitry for queuing snooping, prioritizing and suspending commands
Assignee: Intel Corp
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Filing: 1995-03-21
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Granted: 1996-09-24
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Expires: 2015-03-21
Abstract
Abstract A method of, and apparatus for, storing and prioritizing among erase block and program word commands is described for a nonvolatile memory device. This prevents the depth of an operation queue responsible for queuing program and erase commands from limiting the number of erase commands that are stored at one time. The first erase command received serves as a place holder, holding a place within the operation queue for all subsequently received erase commands. All subsequently received erase commands are absorbed and cleared from the operation queue. As a result, the operation queue may receive additional commands and an erase command may be queued for every block of memory within the nonvolatile memory device. Absorbed erase commands can be prioritized in response to subsequently received program commands. Blocks are flagged for priority erasure using a priority register. Additionally, interrupt windows located at safe points permit interruption of erase operations to handle command interrupts. The erasure of one or more blocks can be suspended so that a program word command can be serviced thereby permitting program word commands to jump ahead of erase block commands in the queue. Furthermore, a query can be made to determine the status of any block and the block status query will consider pending commands in the operation queue when determining the block status for the block queried.
Inventors
- 👤 Richard J. Durante
- 👤 Rodney R. Rozman
- 👤 Mickey L. Fandrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:40
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G06F3/0628; G06F3/0662; G06F3/0664
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
207 words
Command queuing circuitry comprising: a primary queue for holding a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue for holding a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; snooping circuitry for examining the second command, without servicing the second command, prior to completion of service of the first command: prioritization circuitry for determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; switching circuitry for suspending service of the first command and permitting service of the second command if the second command has a higher priority; and command absorption circuitry to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 2
Dependent Claim
207 words
Command queuing circuitry comprising: a primary queue for holding a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue for holding a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; snooping circuitry for examining the second command, without servicing the second command, prior to completion of service of the first command: prioritization circuitry for determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; switching circuitry for suspending service of the first command and permitting service of the second command if the second command has a higher priority; and command absorption circuitry to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 3
Dependent Claim
82 words
The command queuing circuitry as set forth in claim 1 further comprising: priority increasing circuitry to increase the priority, with respect to a first pending erase block erasure, of erasure of an erase-pending erase block specified by a second pending erase block erasure, if the second command is the first program word command and the second command is specifying a flash memory word to be programmed that is part of the erase-pending erase block specified by the second pending erase block erasure.
Claim 4
Dependent Claim
62 words
The command queuing circuitry as set forth in claim 1 further comprising: slot toggle circuitry to override the primary and secondary queue designations so that the primary queue becomes the secondary queue and the secondary queue becomes the primary queue in the event that service of the first command completes while a pending second command is being held in the secondary queue.
Claim 5
Dependent Claim
65 words
The command queuing circuitry as set forth in claim 1 wherein each pending command affects the status of a corresponding erase block of the flash memory, the command queuing circuitry further comprising: block status circuitry to determine whether any commands within the queue affect the status of a query block, the query block being a designated one of the erase blocks of the flash memory.
Claim 6
Dependent Claim
134 words
The command queuing circuitry as set forth in claim 4 wherein the block status circuitry further comprises: pending command query circuitry to determine whether any pending commands affect the status of the query block and to provide a pending status signal that indicates the status of the query block with respect to the pending commands; currently servicing query circuitry to determine whether the command currently being serviced affects the status of the query block and to provide a servicing status signal that indicates the status of the query block with respect to the servicing command; and, integration circuitry to combine the pending status signal and the currently servicing status signal to form a query block status signal that indicates the status of the query block with respect to all commands within the command queue.
Claim 7
Dependent Claim
35 words
The command queuing circuitry as set forth in claim 1 further comprising: a temporary queue to hold at least one command received subsequently to the first and second commands until the secondary queue becomes available.
Claim 8
Dependent Claim
27 words
The command queuing circuitry as set forth in claim 1 wherein the primary queue can receive a second program word command if the primary queue is empty.
Claim 9
Dependent Claim
207 words
Command queuing circuitry comprising: a primary queue to hold a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue to hold a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; a snooper to examine the second command, without servicing the second command, prior to completion of service of the first command; a prioritizer to determine the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; a switch to suspend service of the first command and permit service of the second command if the second command has a higher priority; and a command absorber to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 10
Dependent Claim
207 words
Command queuing circuitry comprising: a primary queue to hold a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue to hold a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; a snooper to examine the second command, without servicing the second command, prior to completion of service of the first command; a prioritizer to determine the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; a switch to suspend service of the first command and permit service of the second command if the second command has a higher priority; and a command absorber to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 11
Dependent Claim
82 words
The command queuing circuitry as set forth in claim 8 further comprising: a priority increaser to increase the priority, with respect to a first pending erase block erasure, of erasure of an erase-pending erase block specified by a second pending erase block erasure, if the second command is the first program word command and the second command is specifying a flash memory word to be programmed that is part of the erase-pending erase block specified by the second pending erase block erasure.
Claim 12
Dependent Claim
62 words
The command queuing circuitry as set forth in claim 8 further comprising: a slot toggler to override the primary and secondary queue designations so that the primary queue becomes the secondary queue and the secondary queue becomes the primary queue in the event that service of the first command completes while a pending second command is being held in the secondary queue.
Claim 13
Dependent Claim
66 words
The command queuing circuitry as set forth in claim 8 wherein each pending command affects the status of a corresponding erase block of the flash memory, the command queuing circuitry further comprising: a block status checker to determine whether any commands within the queue affect the status of a query block, the query block being a designated one of the erase blocks of the flash memory.
Claim 14
Dependent Claim
137 words
The command queuing circuitry as set forth in claim 11 wherein the block status circuitry further comprises: a pending command query checker to determine whether any pending commands affect the status of the query block and to provide a pending status signal that indicates the status of the query block with respect to the pending commands; a currently servicing query checker to determine whether the command currently being serviced affects the status of the query block and to provide a servicing status signal that indicates the status of the query block with respect to the servicing command; and, a status integrator to combine the pending status signal and the currently servicing status signal to form a query block status signal that indicates the status of the query block with respect to all commands within the command queue.
Claim 15
Dependent Claim
35 words
The command queuing circuitry as set forth in claim 8 further comprising: a temporary queue to hold at least one command received subsequently to the first and second commands until the secondary queue becomes available.
Claim 16
Dependent Claim
27 words
The command queuing circuitry as set forth in claim 8 wherein the primary queue can receive a second program word command if the primary queue is empty.
Claim 17
Dependent Claim
202 words
A command queuing method, comprising the steps of: holding a first command in a primary queue, the first command being an erase block command specifying a first flash memory block to be erased; holding a second command, received subsequent to the first command, in a secondary queue, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; examining the second command, without servicing the second command, prior to completion of service of the first command; determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; suspending service of the first command and permitting service of the second command, if the second command has a higher priority than the first command; and incorporating service of the second command into service of the first command and then purging the second command from the secondary queue, if the second command is the second erase flash block command.
Claim 18
Dependent Claim
202 words
A command queuing method, comprising the steps of: holding a first command in a primary queue, the first command being an erase block command specifying a first flash memory block to be erased; holding a second command, received subsequent to the first command, in a secondary queue, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; examining the second command, without servicing the second command, prior to completion of service of the first command; determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; suspending service of the first command and permitting service of the second command, if the second command has a higher priority than the first command; and incorporating service of the second command into service of the first command and then purging the second command from the secondary queue, if the second command is the second erase flash block command.
Claim 19
Dependent Claim
81 words
The command queuing method as set forth in claim 15 further comprising the step of: increasing the priority, with respect to a first pending erase block erasure, of erasure of an erase-pending erase block specified by a second pending erase block erasure, if the second command is the first program word command and the second command is specifying a flash memory word to be programmed that is part of the erase-pending erase block specified by the second pending erase block erasure.
Claim 20
Dependent Claim
61 words
The command queuing method as set forth in claim 15 further comprising the step of: overriding the primary and secondary queue designations so that the primary queue becomes the secondary queue and the secondary queue becomes the primary queue in the event that service of the first command completes while a pending second command is being held in the secondary queue.
Claim 21
Dependent Claim
64 words
The command queuing method as set forth in claim 15 wherein each pending command affects the status of a corresponding erase block of the flash memory, the command queuing method further comprising the step of: determining whether any commands within the queue affect the status of a query block, the query block being a designated one of the erase blocks of the flash memory.
Claim 22
Dependent Claim
124 words
The command queuing method as set forth in claim 18 wherein the block status query step further comprises the steps of: determining whether any pending commands affect the status of the query block and to providing a pending status signal that indicates the status of the query block with respect to the pending commands; determining whether the command currently being serviced affects the status of the query block and providing a servicing status signal that indicates the status of the query block with respect to the servicing command; and, combining the pending status signal and the currently servicing status signal to form a query block status signal that indicates the status of the query block with respect to all commands within the command queue.
Claim 23
Dependent Claim
34 words
The command queuing method as set forth in claim 15 further comprising the step of: holding at least one command received subsequently to the first and second commands until the secondary queue becomes available.
Claim 24
Dependent Claim
31 words
The command queuing method as set forth in claim 15 further comprising the step of: receiving a second program word command in the primary queue if the primary queue is empty.
Claim 25
Independent Claim
240 words
A system comprising: a command issuing device for issuing flash memory program and erase commands; a command servicing device for servicing the program and erase commands issued by the command issuing device; and command queuing circuitry, including: a primary queue for holding a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue for holding a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; snooping circuitry for examining the second command, without servicing the second command, prior to completion of service of the first command; prioritization circuitry for determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; switching circuitry for suspending service of the first command and permitting service of the second command if the second command has a higher priority; and command absorption circuitry to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 26
Independent Claim
240 words
A system comprising: a command issuing device for issuing flash memory program and erase commands; a command servicing device for servicing the program and erase commands issued by the command issuing device; and command queuing circuitry, including: a primary queue for holding a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue for holding a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; snooping circuitry for examining the second command, without servicing the second command, prior to completion of service of the first command; prioritization circuitry for determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; switching circuitry for suspending service of the first command and permitting service of the second command if the second command has a higher priority; and command absorption circuitry to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.
Claim 27
Dependent Claim
80 words
The system as set forth in claim 22 further comprising: priority increasing circuitry to increase the priority, with respect to a first pending erase block erasure, of erasure of an erase-pending erase block specified by a second pending erase block erasure, if the second command is the first program word command and the second command is specifying a flash memory word to be programmed that is part of the erase-pending erase block specified by the second pending erase block erasure.
Claim 28
Dependent Claim
60 words
The system as set forth in claim 22 further comprising: slot toggle circuitry to override the primary and secondary queue designations so that the primary queue becomes the secondary queue and the secondary queue becomes the primary queue in the event that service of the first command completes while a pending second command is being held in the secondary queue.
Claim 29
Dependent Claim
63 words
The system as set forth in claim 22 wherein each pending command affects the status of a corresponding erase block of the flash memory, the command queuing circuitry further comprising: block status circuitry to determine whether any commands within the queue affect the status of a query block, the query block being a designated one of the erase blocks of the flash memory.
Claim 30
Dependent Claim
132 words
The system as set forth in claim 25 wherein the block status circuitry further comprises: pending command query circuitry to determine whether any pending commands affect the status of the query block and to provide a pending status signal that indicates the status of the query block with respect to the pending commands; currently servicing query circuitry to determine whether the command currently being serviced affects the status of the query block and to provide a servicing status signal that indicates the status of the query block with respect to the servicing command; and, integration circuitry to combine the pending status signal and the currently servicing status signal to form a query block status signal that indicates the status of the query block with respect to all commands within the command queue.
Claim 31
Dependent Claim
33 words
The system as set forth in claim 22 further comprising: a temporary queue to hold at least one command received subsequently to the first and second commands until the secondary queue becomes available.
Claim 32
Dependent Claim
25 words
The system as set forth in claim 22 wherein the primary queue can receive a second program word command if the primary queue is empty.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |