US5560032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-03-01
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Granted: 1996-09-24
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Expires: 2015-03-01
Abstract
Abstract A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit. The architecture also optimizes the scheduling of data paths in accordance with the type of computational function, including integer, floating point, and boolean.
Inventors
- 👤 Le Trong Nguyen
- 👤 Derek J. Lentz
- 👤 Yoshiyuki Miyayama
- 👤 Sanjiv Garg
- 👤 Yasuaki Hagiwara
- 👤 Johannes Wang
- 👤 Te-Li Lau
- 👤 Sze-Shun Wang
- 👤 Quang H. Trang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:58
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/30098; G06F9/30101; G06F9/30105; G06F9/30112; G06F9/30116; G06F9/3012; G06F9/30123; G06F9/3013; G06F9/30134; G06F9/30141; G06F9/32; G06F9/322; G06F9/323; G06F9/327; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3814; G06F9/3824; G06F9/3826; G06F9/3828; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3853; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3865; G06F9/3885
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
177 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.
Claim 2
Dependent Claim
177 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.
Claim 3
Dependent Claim
194 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.
Claim 4
Dependent Claim
194 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.
Claim 5
Dependent Claim
47 words
The superscalar processing system according to claim 2, further comprising a load/store unit, wherein said set of parallel buses further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit stores said further distributed results to a memory unit.
Claim 6
Dependent Claim
29 words
The superscalar processing system according to claim 3, wherein said load/store unit loads data into at least one of said floating point register file and said integer register file.
Claim 7
Dependent Claim
29 words
The superscalar processing system according to claim 3, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.
Claim 8
Dependent Claim
212 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and a integer functional unit, and said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.
Claim 9
Dependent Claim
212 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and a integer functional unit, and said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.
Claim 10
Dependent Claim
45 words
The superscalar processing system according to claim 6, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit stores said further transferred results to a memory unit.
Claim 11
Dependent Claim
30 words
The superscalar processing system according to claim 7, wherein said load/store unit loads data into one of said floating point register, said integer register file and said boolean register file.
Claim 12
Dependent Claim
27 words
The superscalar processing system according to claim 7, wherein said load/store unit loads data into one of said floating point functional units and said integer functional units.
Claim 13
Dependent Claim
163 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said second means transfers at least one operand from a floating point register file to an integer functional unit.
Claim 14
Dependent Claim
163 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said second means transfers at least one operand from a floating point register file to an integer functional unit.
Claim 15
Dependent Claim
228 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.
Claim 16
Dependent Claim
228 words
A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.
Claim 17
Dependent Claim
44 words
The superscalar processing system according to claim 11, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit further distributes said results to a memory unit.
Claim 18
Dependent Claim
33 words
The superscalar processing system according to claim 12, wherein said load/store unit loads data into at least one of said floating point register file, said integer register file and said boolean register file.
Claim 19
Dependent Claim
29 words
The superscalar processing system according to claim 12, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.
Claim 20
Independent Claim
160 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; distributing floating point results to an integer file; and distributing integer results to a floating point register file using a set of parallel buses, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
Claim 21
Independent Claim
160 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; distributing floating point results to an integer file; and distributing integer results to a floating point register file using a set of parallel buses, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
Claim 22
Dependent Claim
24 words
The method according to claim 15, further comprising the step of distributing said floating point results and said integer results to a load/store unit.
Claim 23
Dependent Claim
20 words
The method according to claim 16, further comprising the step of storing said further distributed results in a memory unit.
Claim 24
Independent Claim
174 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; transferring floating point results to one of a integer file and a boolean register file; and transferring integer results to one of said floating point register file and said boolean register file using a set of parallel buses, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
Claim 25
Independent Claim
174 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; transferring floating point results to one of a integer file and a boolean register file; and transferring integer results to one of said floating point register file and said boolean register file using a set of parallel buses, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
Claim 26
Dependent Claim
24 words
The method according to claim 18, further comprising the step of distributing said floating point results and said integer results to a load/store unit.
Claim 27
Dependent Claim
20 words
The method according to claim 19, further comprising the step of storing said further distributed results in a memory unit.
Claim 28
Dependent Claim
242 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and wherein said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.
Claim 29
Dependent Claim
242 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and wherein said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.
Claim 30
Dependent Claim
43 words
The computer system according to claim 21, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit further distributes said results to a memory unit.
Claim 31
Dependent Claim
32 words
The computer system according to claim 22, wherein said load/store unit loads data into at least one of said floating point register file, said integer register file and said boolean register file.
Claim 32
Dependent Claim
28 words
The computer system according to claim 22, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.
Claim 33
Dependent Claim
190 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.
Claim 34
Dependent Claim
190 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.
Claim 35
Dependent Claim
207 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.
Claim 36
Dependent Claim
207 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.
Claim 37
Dependent Claim
225 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.
Claim 38
Dependent Claim
225 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and an integer functional unit, and said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.
Claim 39
Dependent Claim
176 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said second means transfers at least one operand from a floating point register file to an integer functional unit.
Claim 40
Dependent Claim
176 words
A computer system, comprising: main memory bus; input/output bus; and a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having: a first stage for decoding and issuing instructions in a prescribed program order; a second stage for executing instructions out-of-order with respect to said prescribed program order; first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said second means transfers at least one operand from a floating point register file to an integer functional unit.
Claim 41
Independent Claim
153 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; and transferring at least one operand from a floating point register file to an integer functional unit, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
Claim 42
Independent Claim
153 words
A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of: storing a source of operands corresponding to a plurality of instruction operations; concurrently transferring said operands to a plurality of functional units; performing said instruction operations to generate results using said plurality of functional units; concurrently distributing said results; and transferring at least one operand from a floating point register file to an integer functional unit, wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |