US5563827A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wordline driver for flash PLD
Assignee: Xilinx Inc
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Filing: 1995-09-25
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Granted: 1996-10-08
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Expires: 2015-09-25
Abstract
Abstract A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.
Inventors
- 👤 Napoleon W. Lee
- 👤 Derek R. Curd
- 👤 Wei-Yi Ku
- 👤 Sholeh Diba
- 👤 George Simmons
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
185 words
A line driver for a first line in an integrated programmable logic device, said line driver comprising: a line input terminal for accepting a binary input signal having a first low logic level and a first high logic level; a pass gate having a first current-handling terminal coupled to said line input terminal, a second current-handling terminal, and a mode-control terminal receiving a mode-control signal, wherein said first current-handling terminal receives said input signal from said line input terminal and wherein said pass gate passes said input signal when said mode-control signal enables said pass gate; an inverter having an input terminal coupled to said second current-handling terminal of said pass gate and having an output terminal, wherein said input terminal receives said input signal and said inverter provides an inverted input signal on said output terminal; and a multiplexer having a first input terminal coupled to said inverter output terminal, said first input terminal for receiving said inverted input signal, a second input terminal coupled to a voltage source, and a line output terminal coupled to said first line of said programmable logic device.
Claim 2
Dependent Claim
185 words
A line driver for a first line in an integrated programmable logic device, said line driver comprising: a line input terminal for accepting a binary input signal having a first low logic level and a first high logic level; a pass gate having a first current-handling terminal coupled to said line input terminal, a second current-handling terminal, and a mode-control terminal receiving a mode-control signal, wherein said first current-handling terminal receives said input signal from said line input terminal and wherein said pass gate passes said input signal when said mode-control signal enables said pass gate; an inverter having an input terminal coupled to said second current-handling terminal of said pass gate and having an output terminal, wherein said input terminal receives said input signal and said inverter provides an inverted input signal on said output terminal; and a multiplexer having a first input terminal coupled to said inverter output terminal, said first input terminal for receiving said inverted input signal, a second input terminal coupled to a voltage source, and a line output terminal coupled to said first line of said programmable logic device.
Claim 3
Dependent Claim
22 words
The line driver of claim 1, wherein said first line of said programmable logic device is coupled to a flash memory cell.
Claim 4
Dependent Claim
62 words
The line driver of claim 2, wherein said flash memory cell includes: an MOS access transistor having a current-handling terminal and having a control terminal coupled to said first line of said programmable logic device; and an EPROM transistor having a current-handling terminal coupled to said current-handling terminal of said access transistor and having a control terminal coupled to a second line.
Claim 5
Dependent Claim
62 words
The line driver of claim 2, wherein said flash memory cell includes: an MOS access transistor having a current-handling terminal and having a control terminal coupled to said first line of said programmable logic device; and an EEPROM transistor having a current-handling terminal coupled to said current-handling terminal of said access transistor and having a control terminal coupled to a second line.
Claim 6
Dependent Claim
48 words
The line driver of claim 1, wherein said pass gate and said inverter are coupled to a power supply voltage V CC supplied directly from a power supply external to said programmable logic device, and wherein said voltage source develops a supply voltage different from V CC .
Claim 7
Dependent Claim
70 words
The line driver of claim 1, wherein a first MOS pass transistor within said pass gate, a pair of complementary MOS transistors in said inverter, and a second MOS pass transistor within said multiplexer comprise a path for conveying said input signal to said line output terminal, and wherein said first and second pass transistors and said complementary MOS transistors have an aspect ratio of greater than 10 to 1.
Claim 8
Dependent Claim
79 words
The line driver of claim 1, wherein said pass gate has a voltage drop between its first and second current-handling terminals such that said input signal on said second current-handling terminal is a binary signal having a second high logic level less than said first high logic level, and wherein said inverter includes a half-latch coupled between said output terminal and said input terminal, said half-latch for raising said second high logic level to said first high logic level.
Claim 9
Dependent Claim
32 words
The line driver of claim 1, further comprising a mode decoder coupled to said mode-control terminal, whereby said mode decoder generates said mode-control signal in response to user inputs to said device.
Claim 10
Dependent Claim
37 words
The line driver of claim 3, wherein said EPROM includes a layer of tunnel oxide, and wherein said second line provides a stress voltage to said control terminal of said EPROM transistor to test said tunnel oxide.
Claim 11
Independent Claim
122 words
A method for driving a line in an integrated programmable logic device having a programming voltage source, said programmable logic device operating in a programming mode and a logic mode, said method comprising the steps of: selecting one of said programming mode and said logic mode; and if said logic mode of operation is selected, providing a binary input signal having a first low logic level and a first high logic level, inverting said input signal, and selecting said inverted input signal and supplying said inverted input signal to said line; and if said programming mode of operation is selected, providing a programming voltage from said programming voltage source, and selecting said programming voltage and coupling said programming voltage to said line.
Claim 12
Independent Claim
122 words
A method for driving a line in an integrated programmable logic device having a programming voltage source, said programmable logic device operating in a programming mode and a logic mode, said method comprising the steps of: selecting one of said programming mode and said logic mode; and if said logic mode of operation is selected, providing a binary input signal having a first low logic level and a first high logic level, inverting said input signal, and selecting said inverted input signal and supplying said inverted input signal to said line; and if said programming mode of operation is selected, providing a programming voltage from said programming voltage source, and selecting said programming voltage and coupling said programming voltage to said line.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |