US5564060A
Expired / Lapsed
US
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Interrupt handling mechanism to prevent spurious interrupts in a symmetrical multiprocessing system
Assignee: GlobalFoundries Inc
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Filing: 1994-05-31
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Granted: 1996-10-08
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Expires: 2014-05-31
Abstract
Abstract A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.
Inventors
- 👤 Rupaka Mahalingaiah
- 👤 Rodney Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:08
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
352 words
A multiprocessing computer system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to generate a respective interrupt signal; a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels coupled to said plurality of processing units, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt; a status register coupled to said central controller configured to store information indicative of whether a particular interrupt signal is idle, wherein said central controller is configured to control the status of said status register according to interrupt signals dispatched to at least one of said plurality of processing units and an End Of Interrupt command executed by said at least one of said plurality of processing units; and a programmable latency timer coupled to said central controller, wherein said central controller is configured to use a value within said programmable latency timer to control a time at which said status register is updated in response to an End Of Interrupt command.
Claim 2
Dependent Claim
352 words
A multiprocessing computer system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to generate a respective interrupt signal; a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels coupled to said plurality of processing units, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt; a status register coupled to said central controller configured to store information indicative of whether a particular interrupt signal is idle, wherein said central controller is configured to control the status of said status register according to interrupt signals dispatched to at least one of said plurality of processing units and an End Of Interrupt command executed by said at least one of said plurality of processing units; and a programmable latency timer coupled to said central controller, wherein said central controller is configured to use a value within said programmable latency timer to control a time at which said status register is updated in response to an End Of Interrupt command.
Claim 3
Dependent Claim
215 words
An interrupt controller comprising: a plurality of interrupt input terminals configured to receive a plurality of interrupt signals; a central controller coupled to said input terminals configured to prioritize said plurality of interrupt signals and configured to provide said interrupt signals to at least one processing unit; an I/O interrupt controller coupled between said plurality of interrupt input terminals and said central controller, said I/O interrupt controller being configured to monitor a status of said plurality of interrupt signals, to selectively respond to an assertion of any of said plurality of interrupt signals and to provide an indication of said assertion to said central controller; a storage unit coupled to said central controller configured to store information indicative of whether a particular interrupt signal is idle, wherein said central controller is configured to control a content of said storage unit according to interrupt signals dispatched to said processing unit and an End Of Interrupt command executed by said processing unit; and a programmable latency timer coupled to said central controller, wherein said central controller is configured to use a value within said programmable latency timer to control a time at which said storage unit is updated in response to an End Of Interrupt command, and wherein said latency timer is programmable through an I/O bus.
Claim 4
Dependent Claim
215 words
An interrupt controller comprising: a plurality of interrupt input terminals configured to receive a plurality of interrupt signals; a central controller coupled to said input terminals configured to prioritize said plurality of interrupt signals and configured to provide said interrupt signals to at least one processing unit; an I/O interrupt controller coupled between said plurality of interrupt input terminals and said central controller, said I/O interrupt controller being configured to monitor a status of said plurality of interrupt signals, to selectively respond to an assertion of any of said plurality of interrupt signals and to provide an indication of said assertion to said central controller; a storage unit coupled to said central controller configured to store information indicative of whether a particular interrupt signal is idle, wherein said central controller is configured to control a content of said storage unit according to interrupt signals dispatched to said processing unit and an End Of Interrupt command executed by said processing unit; and a programmable latency timer coupled to said central controller, wherein said central controller is configured to use a value within said programmable latency timer to control a time at which said storage unit is updated in response to an End Of Interrupt command, and wherein said latency timer is programmable through an I/O bus.
Claim 5
Dependent Claim
32 words
An interrupt controller as recited in claim 2 wherein said central controller is configured to reset a particular interrupt to an idle state a predetermined time after said End Of Interrupt command.
Claim 6
Dependent Claim
35 words
An interrupt controller as recited in claim 2 wherein said I/O interrupt controller is configured to monitor the status of an interrupt if said storage unit indicates that said interrupt is in an idle state.
Claim 7
Dependent Claim
49 words
An interrupt controller as recited in claim 2 further including a processor interrupt generator coupled to said central controller, said processor interrupt generator including a plurality of interrupt output terminals coupled to a plurality of processing units and configured to dispatch interrupt signals to said plurality of processing units.
Claim 8
Dependent Claim
51 words
An interrupt controller as recited in claim 2 further including a decoder coupled between an I/O bus and said programmable latency timer, said decoder being configured to detect an End Of Interrupt command and of enabling said programmable latency timer in response to the detection of said End Of Interrupt command.
Claim 9
Dependent Claim
16 words
An interrupt controller as recited in claim 2, wherein said storage unit is a status register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |