Laminated complementary thin film transistor device with improved threshold adaptability

Claim 2

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6), a source electrode (4), and a drain electrode (5) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) formed on said insulating substrate (1) and disposed under said lower channel (6), said lower gate electrode (2) extending beyond the area of said lower channel (6), said source electrode (4), and said drain electrode (5); an intermediate gate electrode (8) disposed between said lower channel (6) and said upper channel (12); and an upper gate electrode (14) disposed over said upper channel (12).

Claim 3

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) disposed between said lower channel (6) and said upper channel (12), said intermediate gate electrode (8) being a substantially exclusive gate electrode for said lower transistor, said intermediate gate electrode (8) having a larger width than said lower gate electrode (2); another intermediate gate electrode (80) formed as a substantially exclusive gate electrode for said upper transistor; and an upper gate electrode (14) disposed over said upper channel (12), said upper gate electrode (14) having a larger width than said another intermediate gate electrode.

Claim 4

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) disposed between said lower channel (6) and said upper channel (12), said intermediate gate electrode (8) being a substantially exclusive gate electrode for said lower transistor, said intermediate gate electrode (8) having a larger width than said lower gate electrode (2); another intermediate gate electrode (80) formed as a substantially exclusive gate electrode for said upper transistor; and an upper gate electrode (14) disposed over said upper channel (12), said upper gate electrode (14) having a larger width than said another intermediate gate electrode.

Claim 5

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) having an overlapping area with respect to said lower gate electrode and disposed between said lower channel (6) and said upper channel (12); and an upper gate electrode (14) disposed over said upper channel (12), wherein said lower transistor comprises: said lower gate electrode (2) being formed on said insulating substrate (1); a gate insulating film (3) deposited on said lower gate electrode (2) and said insulating substrate (1); a semiconductive layer (4,5,6) deposited on said gate insulating film (3), said semiconductive layer (4,5,6) including a lower source electrode (4) and a lower drain electrode (5), with said lower channel (6) interposed therebetween; another gate insulating film (7) formed on said lower channel (6); and said intermediate gate electrode (8) being formed on said another gate insulating film (7).

Claim 6

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) having an overlapping area with respect to said lower gate electrode and disposed between said lower channel (6) and said upper channel (12); and an upper gate electrode (14) disposed over said upper channel (12), wherein said lower transistor comprises: said lower gate electrode (2) being formed on said insulating substrate (1); a gate insulating film (3) deposited on said lower gate electrode (2) and said insulating substrate (1); a semiconductive layer (4,5,6) deposited on said gate insulating film (3), said semiconductive layer (4,5,6) including a lower source electrode (4) and a lower drain electrode (5), with said lower channel (6) interposed therebetween; another gate insulating film (7) formed on said lower channel (6); and said intermediate gate electrode (8) being formed on said another gate insulating film (7).

Claim 7

A thin film transistor device as claimed in claim 3, wherein: said intermediate gate electrode (8) has an overlapping area with respect to said lower gate electrode (2); and said combination of said lower transistor and said upper transistor includes another intermediate gate electrode (80) having an offset area with respect to said lower gate electrode (2).

Claim 8

A thin film transistor device as claimed in claim 3 wherein said upper gate electrode has an overlapping area with respect to said intermediate gate electrode.

Claim 9

A thin film transistor device as claimed in claim 4 wherein said intermediate gate electrode (80) is formed on a gate insulating film on the gate electrode (8).

Claim 10

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) disposed between said lower channel (6) and said upper channel (12); and an upper gate electrode (14) having an overlapping area with respect to said intermediate gate electrode disposed over said upper channel (12), wherein said lower transistor comprises: said intermediate gate electrode (8); a gate insulating film (9) deposited on said intermediate gate electrode (8) and said lower transistor; a semiconductive layer (10,11,12) deposited on said gate insulating film (9), said semiconductive layer (10,11,12) including an upper source electrode (10) and an upper drain electrode (11), with said upper channel (12) interposed therebetween; another gate insulating film (13) formed on said upper channel (12); and said upper gate electrode (14) being formed on said another gate insulating film (13).

Claim 11

A laminated complementary thin film transistor device comprising: an insulating substrate (1); and a combination of a lower thin film transistor formed on said insulating substrate and an upper thin film transistor laminated over said lower transistor, said combination of said lower transistor and said upper transistor having: a lower channel (6) formed in said lower transistor; an upper channel (12) formed in said upper transistor; a lower gate electrode (2) disposed under said lower channel (6); an intermediate gate electrode (8) disposed between said lower channel (6) and said upper channel (12); and an upper gate electrode (14) having an overlapping area with respect to said intermediate gate electrode disposed over said upper channel (12), wherein said lower transistor comprises: said intermediate gate electrode (8); a gate insulating film (9) deposited on said intermediate gate electrode (8) and said lower transistor; a semiconductive layer (10,11,12) deposited on said gate insulating film (9), said semiconductive layer (10,11,12) including an upper source electrode (10) and an upper drain electrode (11), with said upper channel (12) interposed therebetween; another gate insulating film (13) formed on said upper channel (12); and said upper gate electrode (14) being formed on said another gate insulating film (13).

Claim 12

A thin film transistor device as claimed in claim 7, wherein: said upper gate electrode (14) has an overlapping area with respect to said intermediate gate electrode (8); and said combination of said lower transistor and said upper transistor includes another intermediate gate electrode (80) having an offset area relative to said upper gate electrode (14).

Claim 13

A thin film transistor device as claimed in claim 8 wherein said upper gate electrode has an overlapping area with respect to said intermediate gate electrode.

Claim 14

A thin film transistor device as claimed in claim 9 wherein said intermediate gate electrode (80) is formed on a gate insulating film on the gate electrode (8).