Audio/video/data component system bus

Claim 3

The method set forth in claim 1 further including: generating a Frame Clock signal having an active state coincident with the duration of respective superpackets, and an inactive state in the absence of superpackets, and wherein the duration of active states is constant but the duration of inactive states is variable; conveying said Frame Clock signal in parallel with said superpackets on said bus for use in receiving said superpackets at ones of respective said components.

Claim 4

The method set forth in claim 2 further including: providing interfaces for selectively coupling said bus to respective said components; and providing control signals to said bus for controlling said interfaces.

Claim 5

The method set forth in claim 3 further including: providing a bus of N conductors, N an integer, wherein two of said N conductors are dedicated to said control signals; providing interfaces which are interposed in cascade connection along said bus that include switch means for interconnecting respective portions of at least some conductors in said bus; and controlling said switch means for isolating sections of at least some conductors in said bus with said control signals.

Claim 8

The method set forth in claim 5 wherein the step of forming said superpackets includes assembling said count value, said playback rate code and said transport packet in the sequence recited.

Claim 9

The method set forth in claim 5 wherein said transport packets consist of N eight-bit-bytes, N an integer and the step of forming said superpackets includes forming respective packets of N plus three eight-bit-bytes.

Claim 10

Apparatus for conveying compressed signal between components of an audio video system comprising: an AVD bus including conductor sections coupled in cascade connection with bus interfaces, respective said conductor sections including a plurality of conductors, at least one of which is reserved for control signals, and respective said interfaces comprising; first and second bi-directional input/output ports for connection to respective conductor sections; an input port connected to a first intermediate node for coupling an output of a component to said AVD bus; an output connected to a second intermediate node for coupling an input of said component to said AVD bus; first and second switch means, responsive to control signals, for selectively respectively coupling corresponding conductors of said first and second bi-directional input/output ports to said first intermediate node; third and fourth switch means, responsive to control signals, for selectively respectively coupling said corresponding conductors of said first and second bi-direction input/output ports to said second intermediate node; and control means for providing said control signals.

Claim 11

Apparatus for conveying compressed signal between components of an audio video system comprising: an AVD bus including conductor sections coupled in cascade connection with bus interfaces, respective said conductor sections including a plurality of conductors, at least one of which is reserved for control signals, and respective said interfaces comprising; first and second bi-directional input/output ports for connection to respective conductor sections; an input port connected to a first intermediate node for coupling an output of a component to said AVD bus; an output connected to a second intermediate node for coupling an input of said component to said AVD bus; first and second switch means, responsive to control signals, for selectively respectively coupling corresponding conductors of said first and second bi-directional input/output ports to said first intermediate node; third and fourth switch means, responsive to control signals, for selectively respectively coupling said corresponding conductors of said first and second bi-direction input/output ports to said second intermediate node; and control means for providing said control signals.

Claim 12

The apparatus set forth in claim 8 wherein said first and second bi-directional input/output ports each include a half duplex transceiver.

Claim 13

An interface for conveying transport packet signals on a bi-directional AVD bus to respective AVD components, said interface comprising: a source of compressed signal occurring in MPEG-like transport packets; a system clock; a modulo M counter for counting pulses of said system clock and providing count values; means for capturing a count value at a predetermined instant associated with a respective MPEG-like transport packet; a formatter, coupled to said source, said means for capturing a count value and said AVD bus, for assembling a superpacket including a captured count value and associated MPEG-like transport packet in mutually exclusive portions of said superpacket, and applying said superpacket to said AVD bus.

Claim 14

An interface for conveying transport packet signals on a bi-directional AVD bus to respective AVD components, said interface comprising: a source of compressed signal occurring in MPEG-like transport packets; a system clock; a modulo M counter for counting pulses of said system clock and providing count values; means for capturing a count value at a predetermined instant associated with a respective MPEG-like transport packet; a formatter, coupled to said source, said means for capturing a count value and said AVD bus, for assembling a superpacket including a captured count value and associated MPEG-like transport packet in mutually exclusive portions of said superpacket, and applying said superpacket to said AVD bus.

Claim 15

The apparatus set forth in claim 10, further including: means, coupled to said AVD bus, for generating a Frame Clock having active states coincident with said superpackets, and inactive states in the absence of superpackets, said active states being of constant duration and said inactive states being of variable duration, said Frame Clock for use by respective said components for detecting said superpackets.

Claim 16

The apparatus set forth in claim 11, further including: a source of playback rate codes coupled to said formatter and wherein said formatter composes superpackets including a captured count value, a playback rate code and an associate transport packet in the order recited.

Claim 17

The apparatus set forth in claim 10 wherein one of said components includes circuitry responsive to said superpackets comprising: a controlled oscillator for providing clock pulses for use by said one of said components; a modulo K counter, K an integer, for counting said clock pulses to provide local count values; means responsive to occurrences of each superpacket on said AVD bus for capturing a current local count value exhibited by said modulo K counter; means coupled to said AVD bus for extracting the count value in each said superpacket; clock control circuitry, responsive to said count value extracted from the superpacket and captured said local count value for generating an oscillator control signal for application to said controlled oscillator to condition said controlled oscillator to provide clock pulses at a desired frequency.

Claim 18

Apparatus for communicating compressed data, occurring in a stream of multiplexed transport packets, amongst component devices, comprising a source of said transport packets, means for generating timestamps associated with respective said transport packets, and means for forming a superpacket including said timestamp and an associated transport packet in mutually exclusive fields of said superpacket, and applying same to a bus interconnecting said component devices.

Claim 19

Apparatus for communicating compressed data, occurring in a stream of multiplexed transport packets, amongst component devices, comprising a source of said transport packets, means for generating timestamps associated with respective said transport packets, and means for forming a superpacket including said timestamp and an associated transport packet in mutually exclusive fields of said superpacket, and applying same to a bus interconnecting said component devices.

Claim 20

The apparatus set forth in claim 14 further including: a buffer memory; an inverse transport processor, coupled to said source of transport packets and responsive to said stream of multiplexed transport packets, for selecting transport packets related to a single program, and applying payloads of selected said transport packets to said buffer memory; and respective signal decompression apparatus, coupled to said buffer memory, for reading selected said payloads form said buffer memory and decompressing program components associated with selected said payloads.

Claim 21

Apparatus for receiving a stream of superpackets, including timestamps and transport packets as described in claim 14 comprising: means for determining the occurrence of said superpackets; means for extracting a timestamp from respective said superpacket; and means responsive to a superpacket and extracted said timestamp for separating a transport packet from said superpacket and providing a substantially jitter free transport packet.