Multi-bit testing circuit for semiconductor memory device

Claim 2

A multi-bit testing circuit for testing a semiconductor memory device having a plurality of memory cells, comprising: a first amplifying means coupled to a first group of memory cells for sensing at least one pair of bit line signals having values complementary to one another, each pair being associated with a respective one of the memory cells of the first group and for providing each of said sensed pair of bit line signals to a respective one of first and second output lines of a common signal path when said first sense amplifying means is activated; a second amplifying means coupled to a second group of memory cells for sensing at least one pair of bit line signals having values complementary to one another, each pair being associated with a respective one of the memory cells of the second group and for providing each of said sensed pair of bit line signals to a respective one of the first and second output lines of said common signal path when said second sense amplifying means is activated; and a third amplifying means coupled to said first and second output lines of said common signal path for producing an output signal in response to said sensed pair of bit line signals provided on the first and second output lines by said first amplifying means and said second amplifying means when activated.

Claim 3

The multi-bit testing circuit of claim 1, further comprising direct sense amplifying means coupled between the first and second amplifying means and the common signal path for receiving said sensed pair of bit line signals from at least one of the first and second amplifying means and for providing said sensed pair of bit line signals onto said common path in response to a column selecting signal.

Claim 4

The multi-bit testing circuit of claim 1, wherein said third amplifying means includes means for indicating whether any of the memory cells sensed by at least one of the first and second amplifying means is defective based on said output signal.

Claim 5

The multi-bit testing circuit of claim 1, wherein said third amplifying means includes means for checking whether said pair of bit line signals provided on said first and second output lines by activated ones of said first amplifying means and said amplifying means are identical to one another and means for determining whether a defective cell is present in the memory device based on a checking result of said checking means.

Claim 6

The multi-bit testing circuit of claim 1, further comprising a plurality of direct sense amplifying means, each corresponding to a column representing the array of memory cells of the memory device and coupled between a respective one of the first and second amplifying means and the common signal path for receiving said sensed pair of bit lines corresponding to said column from said respective one of the first and second amplifying means and for providing said sensed pair of bit lines to said first and second output lines of the common signal path.

Claim 7

The multi-bit testing circuit of claim 1, wherein said third amplifying means includes: a first transistor means for receiving a first signal from the first output line; a second transistor means for receiving a second signal from the second output line; a first current control means coupled to said first transistor means for providing a first current corresponding to the first signal; a second current control means coupled to said second transistor means for providing a second current corresponding to the second signal; and a means coupled to said first and second current control means for providing an output signal based on said first and second currents.

Claim 8

The multi-bit testing circuit of claim 1, wherein said third amplifying means includes: a current mirror circuit; a first MOS transistor coupled to said current mirror circuit for receiving a signal from the first output line; a second MOS transistor coupled to said current mirror circuit for receiving a signal from said second output line; and a third MOS transistor coupled to said current mirror for receiving a reference signal.

Claim 9

The multi-bit testing circuit of claim 2, wherein said direct sense amplifying means includes a first pair of MOS transistors connected in series with respect to one another, and a second pair of MOS transistors connected in series with respect to one another, said first and second pairs being connected in parallel with respect to one another, each of said first and second pairs being coupled to a respective one of said sensed pair of bit lines and a respective one of said first and second output lines.

Claim 10

The multi-bit testing circuit of claim 6, wherein said second transistor means includes means for receiving a reference signal, and wherein said second current control means includes means for providing said second current based on said second signal and said reference signal.

Claim 11

A multi-bit testing circuit for testing a semiconductor memory device having a plurality of memory cells, comprising: a plurality of first amplifying means coupled to said plurality of memory cells for sensing one or more pairs of bit line signals corresponding to a column selection signal; a direct sense amplifier (DSA) circuit coupled to said plurality of first amplifying means for providing said sensed one or more pairs of bit line signals on a common signal path having first and second output lines; and a second amplifying means coupled to said common signal path for providing an output signal based on the sensed one or more pairs of bit line signals provided on said first and second output lines.

Claim 12

A multi-bit testing circuit for testing a semiconductor memory device having a plurality of memory cells, comprising: a plurality of first amplifying means coupled to said plurality of memory cells for sensing one or more pairs of bit line signals corresponding to a column selection signal; a direct sense amplifier (DSA) circuit coupled to said plurality of first amplifying means for providing said sensed one or more pairs of bit line signals on a common signal path having first and second output lines; and a second amplifying means coupled to said common signal path for providing an output signal based on the sensed one or more pairs of bit line signals provided on said first and second output lines.

Claim 13

A multi-bit testing circuit for a semiconductor memory device, comprising: a first sensing section comprising a sense amplifier connected to a memory cell of the semiconductor memory device to receive bit line signals therefrom, and a direct sense amplifier (DSA) circuit for receiving the bit line signals from the sense amplifier and column selecting signals so as to output the bit line signals as signals S and S; and a second sensing section for receiving the signals S and S from the first sensing section and for producing a first output signal, indicating a normal semiconductor memory device, when the signals S and S have values complementary to one another, and for producing a second output signal, indicating a defective semiconductor memory device, when the signals S and S have a same signal level.

Claim 14

A multi-bit testing circuit for a semiconductor memory device, comprising: a first sensing section comprising a sense amplifier connected to a memory cell of the semiconductor memory device to receive bit line signals therefrom, and a direct sense amplifier (DSA) circuit for receiving the bit line signals from the sense amplifier and column selecting signals so as to output the bit line signals as signals S and S; and a second sensing section for receiving the signals S and S from the first sensing section and for producing a first output signal, indicating a normal semiconductor memory device, when the signals S and S have values complementary to one another, and for producing a second output signal, indicating a defective semiconductor memory device, when the signals S and S have a same signal level.

Claim 15

The circuit as claimed in claim 11, wherein the DSA circuit comprises a pair of first MOS transistors for receiving the bit line signals, and a second MOS transistor, connected to the pair of first MOS transistors in series, and having a gate for receiving the column selecting signals, whereby the second MOS transistor is turned on by the column selecting signals to allow the pair of first MOS transistors to transmit the bit line signals as the signals S and S.

Claim 16

The circuit as claimed in claim 11, wherein the second sensing section comprises first and second sets of elements; the first set of elements comprising a first current mirror circuit, first parallel-connected MOS transistors connected to the first current mirror circuit and receiving the signal S from the first sensing section, a second MOS transistor connected to the first current mirror circuit and receiving the signal S from the first sensing section, and a third MOS transistor connected to the first current mirror circuit and receiving a reference signal; and the second set of elements comprising a second current mirror circuit, fourth parallel-connected MOS transistors connected to the second current mirror circuit and receiving the signal S from the first sensing section, a fifth MOS transistor connected to the second current mirror circuit and receiving the signal S from the first sensing section, and a sixth MOS transistor connected to the second current mirror circuit and receiving the reference signal; whereby the first and second output signals are outputted from the second sensing section at a node commonly connected to the first current mirror circuit, the second MOS transistor, and the third MOS transistor, and at a node commonly connected to the second current mirror circuit, the fifth MOS transistor, and the sixth HOS transistor.

Claim 17

A multi-bit testing circuit for a semiconductor memory device, comprising: a first sense amplifier for receiving bit line signals from memory cells of the semiconductor memory device; a direct sense amplifier (DSA) circuit for outputting said bit line signals from the first sense amplifier as signals S and S onto a data bus line; and a second sense amplifier connected to the data bus line for producing amplified signals S and S; whereby the memory cells of the semiconductor memory device are determined to be normal or defective based on values of the amplified signals S and S.

Claim 18

A multi-bit testing circuit for a semiconductor memory device, comprising: a first sense amplifier for receiving bit line signals from memory cells of the semiconductor memory device; a direct sense amplifier (DSA) circuit for outputting said bit line signals from the first sense amplifier as signals S and S onto a data bus line; and a second sense amplifier connected to the data bus line for producing amplified signals S and S; whereby the memory cells of the semiconductor memory device are determined to be normal or defective based on values of the amplified signals S and S.

Claim 19

The circuit as claimed in claim 14, wherein said second sense amplifier comprises first and second sets of elements; the first set of elements comprising a first current mirror circuit, parallel-connected MOS transistors connected to the first current mirror circuit and receiving the signal S from the DSA circuit, a MOS transistor connected to the first current mirror circuit and receiving the signal S from the DSA circuit, and a MOS transistor connected to the first current mirror circuit and receiving a reference signal; and the second set of elements comprising a second current mirror circuit, parallel-connected MOS transistors connected to the second current mirror circuit and receiving the signal S from the DSA circuit, a MOS transistor connected to the second current mirror circuit and receiving the signal S from the DSA circuit, and a MOS transistor connected to the second current mirror circuit and receiving the reference signal.

Claim 20

The circuit as claimed in claim 14, wherein said DSA circuit comprises a pair of MOS transistors for receiving the bit line signals, and a MOS transistor, connected to the pair of MOS transistors in series, and having a gate for receiving column selecting signals, whereby the MOS transistor is turned on by the column selecting signals to allow the pair of MOS transistors to output the bit line signals onto the data bus line as the signals S and S.