US5572437A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
Assignee: LSI Corp
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Filing: 1994-05-20
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Granted: 1996-11-05
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Expires: 2014-05-20
Abstract
Abstract An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.
Inventors
- 👤 Michael D. Rostoker
- 👤 Carlos Dangelo
- 👤 Owen S. Bair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:42
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/31704; G01R31/318364; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
51 words
A method of verifying a logic model of an electronic design, in an ECAD system, comprising: providing a logic-level model of the electronic design; obtaining timing and delay information obtained from a transistor-level model simulation of the design; and providing the timing and delay information to the logic-level model for simulation.
Claim 2
Independent Claim
51 words
A method of verifying a logic model of an electronic design, in an ECAD system, comprising: providing a logic-level model of the electronic design; obtaining timing and delay information obtained from a transistor-level model simulation of the design; and providing the timing and delay information to the logic-level model for simulation.
Claim 3
Independent Claim
70 words
A method of creating and validating a structural description of an electronic design from a behavioral description thereof, comprising: providing a behavioral description of the electronic design; simulating and changing the behavioral description of the design; partitioning the behavioral description into a number of architectural blocks and constraining the architectural choices to those which meet high-level timing goals; and synthesizing the architectural blocks into a structural description of the design.
Claim 4
Independent Claim
70 words
A method of creating and validating a structural description of an electronic design from a behavioral description thereof, comprising: providing a behavioral description of the electronic design; simulating and changing the behavioral description of the design; partitioning the behavioral description into a number of architectural blocks and constraining the architectural choices to those which meet high-level timing goals; and synthesizing the architectural blocks into a structural description of the design.
Claim 5
Independent Claim
57 words
A method of creating an electronic design on an ECAD system, comprising: synthesizing a physical description of the electronic design from a behavioral description of the electronic system; generating an interim logic-level model representation of the design; and simulating the logic-level model representation of the electronic system using information derived from the physical description of the design.
Claim 6
Independent Claim
57 words
A method of creating an electronic design on an ECAD system, comprising: synthesizing a physical description of the electronic design from a behavioral description of the electronic system; generating an interim logic-level model representation of the design; and simulating the logic-level model representation of the electronic system using information derived from the physical description of the design.
Claim 7
Independent Claim
59 words
A method of designing an electronic system on an ECAD system, comprising: synthesizing a physical description of the electronic system from a behavioral description of the electronic system, generating an interim logic-level model representation of the electronic system; and simulating the logic-level model representation of the electronic system using information derived from the physical description of the electronic system.
Claim 8
Independent Claim
59 words
A method of designing an electronic system on an ECAD system, comprising: synthesizing a physical description of the electronic system from a behavioral description of the electronic system, generating an interim logic-level model representation of the electronic system; and simulating the logic-level model representation of the electronic system using information derived from the physical description of the electronic system.
Claim 9
Dependent Claim
141 words
An electronic design system comprising: means for creating a net-list description of an electronic design from a behavioral description of the design; means for analyzing the behavioral description for input-to-output dependencies corresponding to logical relationships between inputs and outputs of said design and for creating a list of the input-to-output dependencies; means for determining input patterns and corresponding output transitions, according to said input-to-output dependencies, and for creating a list of the input patterns; means for performing a circuit-level simulation of the design according to said lists of input-to-output dependencies and input patterns; means for extracting delay and timing information from the circuit-level simulation of the design; means for performing a gate-level simulation of the design, using the extracted delay and timing information, and for creating a logic-level model the design; and means for simulating the logic-level model of the design.
Claim 10
Dependent Claim
141 words
An electronic design system comprising: means for creating a net-list description of an electronic design from a behavioral description of the design; means for analyzing the behavioral description for input-to-output dependencies corresponding to logical relationships between inputs and outputs of said design and for creating a list of the input-to-output dependencies; means for determining input patterns and corresponding output transitions, according to said input-to-output dependencies, and for creating a list of the input patterns; means for performing a circuit-level simulation of the design according to said lists of input-to-output dependencies and input patterns; means for extracting delay and timing information from the circuit-level simulation of the design; means for performing a gate-level simulation of the design, using the extracted delay and timing information, and for creating a logic-level model the design; and means for simulating the logic-level model of the design.
Claim 11
Dependent Claim
28 words
An electronic design system, according to claim 5, further comprising: means for simulating a switch-level representation of the design; and means for comparing the switch-level and logic-level simulations.
Claim 12
Dependent Claim
32 words
An electronic design system, according to claim 5, further comprising: means for providing information from the simulated logic-level model of the design in human-readable form in the form of a data sheet.
Claim 13
Dependent Claim
30 words
An electronic design system, according to claim 5, further comprising: means for combining the timing information into the logic-level model to produce a single multi-mode logic model of the design.
Claim 14
Dependent Claim
55 words
An electronic design system, according to claim 5, further comprising: means for automatically generating a translated test pattern file; means for automatically generating a multi-mode file; means for running a comparison simulation using the test pattern file and the multi-mode file; and means for comparing the results of the circuit-level simulation with the comparison simulation.
Claim 15
Dependent Claim
98 words
An automatic logic model generation system comprising: means for operating on inputs and storing a net-list representation of an electronic design; means for simulating performance of a logic-level model of the design as interconnected logic blocks; means for simulating performance of a transistor-level model of the design; means for providing layout information to the transistor-level model of the design; means for providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and means for synthesizing a physical description of the electronic system from a behavioral description of the electronic system.
Claim 16
Dependent Claim
98 words
An automatic logic model generation system comprising: means for operating on inputs and storing a net-list representation of an electronic design; means for simulating performance of a logic-level model of the design as interconnected logic blocks; means for simulating performance of a transistor-level model of the design; means for providing layout information to the transistor-level model of the design; means for providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and means for synthesizing a physical description of the electronic system from a behavioral description of the electronic system.
Claim 17
Dependent Claim
47 words
An automatic model generation system, according to claim further comprising: means for simulating a switch-level representation of the design; means for comparing the logic-level simulation with the switch-level simulation, according to pre-determined criteria for success; and means for providing an indication of a result of said comparison.
Claim 18
Dependent Claim
27 words
An automatic model generation system, according to claim 10, further comprising: means for providing timing and delay information obtained for the transistor-level simulation to the switch-level model.
Claim 19
Dependent Claim
22 words
An automatic model generation system, according to claim 10, further comprising: means for providing said logic-level model in a human-readable data-sheet form.
Claim 20
Dependent Claim
91 words
Method of generating logic and timing models in an ECAD system, comprising: operating on inputs and storing a net-list representation of an electronic design; simulating performance of a logic-level model of the design as interconnected logic blocks; simulating performance of a transistor-level model of the design; providing layout information to the transistor-level model of the design; providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and synthesizing a physical description of the electronic system from a behavioral description of the electronic system.
Claim 21
Dependent Claim
91 words
Method of generating logic and timing models in an ECAD system, comprising: operating on inputs and storing a net-list representation of an electronic design; simulating performance of a logic-level model of the design as interconnected logic blocks; simulating performance of a transistor-level model of the design; providing layout information to the transistor-level model of the design; providing timing and delay information obtained from the simulated performance of the transistor-level model to the logic blocks; and synthesizing a physical description of the electronic system from a behavioral description of the electronic system.
Claim 22
Dependent Claim
42 words
An automatic model generation system, according to claim 14 further comprising: simulating a switch-level representation of the design; comparing the logic-level simulation with the switch-level simulation, according to pre-determined criteria for success; and providing an indication of a result of said comparison.
Claim 23
Dependent Claim
25 words
An automatic model generation system, according to claim 14, further comprising: providing timing and delay information obtained for the transistor-level simulation to the switch-level model.
Claim 24
Dependent Claim
20 words
An automatic model generation system, according to claim 13, further comprising: providing said logic-level model in a human-readable data-sheet form.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |