Nonvolatile semiconductor storage system

Claim 2

A nonvolatile semiconductor storage system comprising: a plurality of memory transistors arranged in a matrix, each of said memory transistors comprising a floating gate electrode, a control gate electrode, a source region and a drain region, the data writing and erasing operations of memory transistors being carried out by injection and release of electrons relative to said floating gate electrode; a plurality of bit lines, the drain region of each memory transistor being connected to one of said bit lines; a source line, the source region of each memory transistor being connected to said source line; a plurality of word lines, the control gate electrode of each memory transistor being connected to one of said word lines; a source line control circuit for applying a first positive voltage to said source line during a reading operation; a bit line control circuit for applying a second positive voltage which is higher than said first positive voltage to at least one bit line of said plurality of bit lines during the reading operation; and means for reducing the threshold voltage difference, during the erasing operation, between the threshold voltage of a memory transistor in which the threshold voltage is most slowly reduced and the threshold voltage of another memory transistor in which the threshold voltage is most rapidly reduced.

Claim 3

A nonvolatile semiconductor storage system as defined in claim 1, further comprising a positive voltage genareting circuit for supplying said first positive voltage to said source line control circuit.

Claim 4

A nonvolatile semiconductor storage system comprising: a plurality of memory transistors arranged in a matrix, each of said memory transistors comprising a floating gate electrode, a control gate electrode, a source region and a drain region, the data writing and erasing operations of memory transistors being carried out by injection and release of electrons relative to said floating gate electrode; a plurality of bit lines, the drain region of each memory transistor being connected to one of said bit lines; a source line, the source region of each memory transistor being connected to said source line; a plurality of word lines, the control gate electrode of each memory transistor being connected to one of said word lines; a source line control circuit for applying a first positive voltage to said source line during a reading operation; a bit line control circuit for applying a second positive voltage which is higher than said first positive voltage to at least one bit line of said plurality of bit lines during the reading operation; and a negative voltage genareting circuit for applying a negative voltage to the substrates of the memory transistors during the reading operation.

Claim 5

A nonvolatile semiconductor storage system comprising: a plurality of memory transistors arranged in a matrix, each of said memory transistors comprising a floating gate electrode, a control gate electrode, a source region and a drain region, the data writing and erasing operations of memory transistors being carried out by injection and release of electrons relative to said floating gate electrode; a plurality of bit lines, the drain region of each memory transistor being connected to one of said bit lines; a source line, the source region of each memory transistor being connected to said source line; a plurality of word lines, the control gate electrode of each memory transistor being connected to one of said word lines; a source line control circuit for applying a first positive voltage to said source line during a reading operation; a bit line control circuit for applying a second positive voltage which is higher than said first positive voltage to at least one bit line of said plurality of bit lines during the reading operation; and a negative voltage genareting circuit for applying a negative voltage to the substrates of the memory transistors during the reading operation.

Claim 6

A nonvolatile semiconductor storage system as defined in claim 3, further comprising means for reducing the threshold voltage difference, during the erasing operation, between the threshold voltage of a memory transistor in which the threshold voltage is most slowly reduced and the threshold voltage of another memory transistor in which the threshold voltage is most rapidly reduced.

Claim 7

A nonvolatile semiconductor storage system as defined in claim 3, further comprising: a positive voltage genareting circuit for supplying said first positive voltage to said source line control circuit.

Claim 8

A nonvolatile semiconductor storage system comprising: a plurality of memory transistors arranged in a matrix, each of said memory transistors comprising a floating gate electrode, a control gate electrode, a source region and a drain region, the data writing and erasing operations of memory transistors being carried out by injection and release of electrons relative to said floating gate electrode; a plurality of bit lines, the drain region of each memory transistor being connected to one of said bit lines; a source line, the source region of each memory transistor being connected to said source line; a plurality of word lines, the control gate electrode of each memory transistor being connected to one of said word lines; a source line control circuit for applying a first positive voltage to said source line during a reading operation; a bit line control circuit for applying a second positive voltage which is higher than said first positive voltage to at least one bit line of said plurality of bit lines during the reading operation; and an x-decoder for applying a positive voltage to at least one word line of said plurality of word lines during a reading operation, the at least one word line connected to a memory transistor subjected to the reading operation and for applying a negative voltage to at least another of said plurality of word lines during the reading operation.

Claim 9

A nonvolatile semiconductor storage system comprising: a plurality of memory transistors arranged in a matrix, each of said memory transistors comprising a floating gate electrode, a control gate electrode, a source region and a drain region, the data writing and erasing operations of memory transistors being carried out by injection and release of electrons relative to said floating gate electrode; a plurality of bit lines, the drain region of each memory transistor being connected to one of said bit lines; a source line, the source region of each memory transistor being connected to said source line; a plurality of word lines, the control gate electrode of each memory transistor being connected to one of said word lines; a source line control circuit for applying a first positive voltage to said source line during a reading operation; a bit line control circuit for applying a second positive voltage which is higher than said first positive voltage to at least one bit line of said plurality of bit lines during the reading operation; and an x-decoder for applying a positive voltage to at least one word line of said plurality of word lines during a reading operation, the at least one word line connected to a memory transistor subjected to the reading operation and for applying a negative voltage to at least another of said plurality of word lines during the reading operation.

Claim 10

A nonvolatile semiconductor storage system as defined in claim 6, further comprising means for reducing the threshold voltage difference, during the erasing operation, between the threshold voltage of a memory transistor in which the threshold voltage is most slowly reduced and the threshold voltage of another memory transistor in which the threshold voltage is most rapidly reduced.

Claim 11

A nonvolatile semiconductor storage system as defined in claim 6, further comprising a negative voltage genareting circuit for applying a negative voltage to the substrates of said memory transistors during the reading operation.

Claim 12

A nonvolatile semiconductor storage system as defined in claim 8, further comprising means for reducing the threshold voltage difference, during the erasing operation, between the threshold voltage of a memory transistor in which the threshold voltage is most slowly reduced and the threshold voltage of another memory transistor in which the threshold voltage is most rapidly reduced.

Claim 13

A nonvolatile semiconductor storage system as defined in claim 6, further comprising: a positive voltage genareting circuit for supplying said first positive voltage to said source line control circuit.