US5574730A
Expired / Lapsed
US
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Bussed test access port interface and method for testing and controlling system logic boards
Assignee: Unisys Corp
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Filing: 1995-01-31
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Granted: 1996-11-12
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Expires: 2015-01-31
Abstract
Abstract Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line. If the instructions or data are intended for a specific system logic board, its corresponding ME signal line will be enabled to permit the passage of these signals and the resulting TDO signal through the interface enable circuit. This arrangement permits the incorporation of a bussed TAP interface into a system control interface for testing and controlling system logic boards that comply fully with the IEEE 1149.1 standard, while conserving the system controller card backplane pins dedicated to TAP signals, to two pins per system logic board plus four pins for the bussed TAP interface.
Inventors
- 👤 Joseph H. End, III
- 👤 Todd M. Rimmer
- 👤 Andrew F. Sanderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
193 words
A system for testing and controlling a plurality of system logic boards, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, the system, comprising: a controller for producing test access port signals and enable signals; a bus coupled between said controller and the plurality of system logic boards for transferring contemporaneously said test access port signals from said controller to each of the plurality of system logic boards, wherein said test access port signals include a test data input signal (TC -- TXD); first signal lines coupled between said controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said controller to at least one of the plurality of system logic boards, wherein said system logic boards are responsive to said test access port signals when said system logic boards receive active enable signals and cause said system logic boards to produce test results signals; and second signal lines coupled between said controller and the plurality of system logic boards, for transferring said test result signals to said controller.
Claim 2
Independent Claim
193 words
A system for testing and controlling a plurality of system logic boards, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, the system, comprising: a controller for producing test access port signals and enable signals; a bus coupled between said controller and the plurality of system logic boards for transferring contemporaneously said test access port signals from said controller to each of the plurality of system logic boards, wherein said test access port signals include a test data input signal (TC -- TXD); first signal lines coupled between said controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said controller to at least one of the plurality of system logic boards, wherein said system logic boards are responsive to said test access port signals when said system logic boards receive active enable signals and cause said system logic boards to produce test results signals; and second signal lines coupled between said controller and the plurality of system logic boards, for transferring said test result signals to said controller.
Claim 3
Dependent Claim
31 words
The system of claim 1, wherein each of said first signal line is a point-to-point electrical connection for transferring said enable signal, wherein said enable signal is a maintenance enable signal.
Claim 4
Dependent Claim
36 words
The system of claim 1, wherein each of said second signal line is a point-to-point electrical connection for transferring said test result signal, wherein said test result signal is a TAP control bus receive data signal.
Claim 5
Dependent Claim
77 words
The system of claim 1, wherein said controller further comprises: a processor, for producing said test access port signals and enable signals; a latch coupled to said processor for receiving and storing logic states of said enable signals; and a multiplexer coupled to said processor and said latch, wherein said multiplexer selects a particular test result signal and passes said selected signal to said processor, based on corresponding logic states stored in said latch that are active.
Claim 6
Dependent Claim
67 words
The system of claim 1, wherein the system logic board further comprises an interface enable circuit coupled to said bus, said first signal line and said second signal line, wherein said interface enable circuit passes said test access port signals to at least one integrated circuit on the system logic board when said enable signal is active causing the system logic board to produce test result signals.
Claim 7
Independent Claim
312 words
A system for testing and controlling a plurality of system logic boards, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, the system, comprising: a first controller for producing test access port signals and enable signals; a second controller for producing test access port signals and enable signals; a first bus coupled between said first controller and the plurality of system logic boards for transferring said test access port signals from said first controller to the plurality of system logic boards; a second bus coupled between said second controller and the plurality of system logic boards for transferring said test access port signals from said second controller to the plurality of system logic boards; first signal lines coupled between said first controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said first controller to at least one of the plurality of system logic boards; second signal lines coupled between said second controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said second controller to at least one of the plurality of system logic boards, wherein said system logic boards are responsive to said test access port signals from at most only one of said busses based on a predefined combination of said active or non-active enable signals from said first controller and said second controller and cause said system logic boards to produce test result signals; third signal lines coupled between said first controller and the plurality of system logic boards, for transferring said test result signals to said first controller; and fourth signal lines coupled between said second controller and the plurality of system logic boards, for transferring said test result signals to said second controller.
Claim 8
Independent Claim
312 words
A system for testing and controlling a plurality of system logic boards, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, the system, comprising: a first controller for producing test access port signals and enable signals; a second controller for producing test access port signals and enable signals; a first bus coupled between said first controller and the plurality of system logic boards for transferring said test access port signals from said first controller to the plurality of system logic boards; a second bus coupled between said second controller and the plurality of system logic boards for transferring said test access port signals from said second controller to the plurality of system logic boards; first signal lines coupled between said first controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said first controller to at least one of the plurality of system logic boards; second signal lines coupled between said second controller and the plurality of system logic boards, for transferring at least one active or non-active enable signal from said second controller to at least one of the plurality of system logic boards, wherein said system logic boards are responsive to said test access port signals from at most only one of said busses based on a predefined combination of said active or non-active enable signals from said first controller and said second controller and cause said system logic boards to produce test result signals; third signal lines coupled between said first controller and the plurality of system logic boards, for transferring said test result signals to said first controller; and fourth signal lines coupled between said second controller and the plurality of system logic boards, for transferring said test result signals to said second controller.
Claim 9
Dependent Claim
36 words
The system of claim 6, wherein each of said first signal line and said second signal line is a point-to-point electrical connection for transferring said enable signal, wherein said enable signal is a maintenance enable signal.
Claim 10
Dependent Claim
41 words
The system of claim 6, wherein each of said third signal line and said fourth signal line is a point-to-point electrical connection for transferring said test result signal, wherein said test result signal is a TAP control bus receive data signal.
Claim 11
Dependent Claim
83 words
The system of claim 6, wherein each of said first controller and second controller further comprises: a processor, for producing said test access port signals and enable signals; a latch coupled to said processor for receiving and storing logic states of said enable signals; and a multiplexer coupled to said processor and said latch, wherein said multiplexer selects a particular test result signal and passes said selected signal to said processor, based on corresponding logic states stored in said latch that are active.
Claim 12
Dependent Claim
89 words
The system of claim 6, wherein the system logic board further comprises an interface enable circuit coupled to said first bus, said second bus, said first signal line, said second signal line, said third signal line and said fourth signal line, wherein said interface enable circuit passes said test access port signals from at most only one of said busses to at least one integrated circuit on the system logic board based on said predefined combination of enable signals, causing the system logic board to produce test result signals.
Claim 13
Dependent Claim
49 words
The system of claim 10, wherein said interface enable circuit further comprises: a first set of interface pins; and a second set of interface pins, wherein said first bus and said second bus are interchangeably coupled to said first set of interface pins or second set of interface pins.
Claim 14
Independent Claim
125 words
A method for testing and controlling a plurality of system logic boards with a controller, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, comprising the step of: (a) transferring at least one active or non-active enable signal to at least one of the plurality of system logic boards; (b) enabling at least one target system logic board with said active enable signal; (c) sending test access port signals from the controller to all system logic boards simultaneously, wherein said test access port signals include a test data input signal (TC -- TXD); and (d) transferring a test result signal from said enabled target system logic board to said controller.
Claim 15
Independent Claim
125 words
A method for testing and controlling a plurality of system logic boards with a controller, each system logic board having at least one integrated circuit which is designed in accordance with conventional test access port and boundary-scan architecture standards, comprising the step of: (a) transferring at least one active or non-active enable signal to at least one of the plurality of system logic boards; (b) enabling at least one target system logic board with said active enable signal; (c) sending test access port signals from the controller to all system logic boards simultaneously, wherein said test access port signals include a test data input signal (TC -- TXD); and (d) transferring a test result signal from said enabled target system logic board to said controller.
Claim 16
Dependent Claim
42 words
A method as recited in claim 12, wherein said enabling step includes the step of enabling an interface enable circuit that passes said test access port signals to said integrated circuit and passes result data from said integrated circuit to said controller.
Claim 17
Dependent Claim
19 words
A method as recited in claim 12, further comprising the step of writing bit values to an enable register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |