US5579322A
Expired / Lapsed
US
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Dual port memory having testing circuit
Assignee: Sony Corp
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Filing: 1994-08-25
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Granted: 1996-11-26
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Expires: 2014-08-25
Abstract
Abstract An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports. The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.
Inventors
- 👤 Takeshi Onodera
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:12
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G11C29/36
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
298 words
An embedded testing circuit of a dual port memory embedded in a semiconductor integrated circuit together with a dual port memory for testing the memory comprising: a first group of scan registers formed of serially connected plural stages of scan registers provided on each port at the address input side of said dual port memory corresponding to each node; an address inputting circuit for selectively supplying predetermined pattern data or their inverted pattern data to one port side of said first group of scan registers and the other of said inverted pattern data or said predetermined pattern data to the other port side of said first group of scan registers; a second group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data input side of said dual port memory corresponding to each node; and a data inputting circuit for selectively supplying said predetermined pattern data or said inverted pattern data passed through the one port side of said first group of scan registers to the one port side of said second group of scan registers and selectively supplying, in a first mode, said inverted pattern data or said predetermined pattern data passed through the other port side of said first group of scan registers, and, in a second mode, said predetermined pattern data or said inverted pattern data passed through the other port side of said first group of scan registers, to the other port side of said second group of scan registers, wherein in said first mode, data written from a port A and data written from a port B are always held in inverse relationship to each other; and wherein in said second mode, the same data can be written from port A and port B.
Claim 2
Dependent Claim
298 words
An embedded testing circuit of a dual port memory embedded in a semiconductor integrated circuit together with a dual port memory for testing the memory comprising: a first group of scan registers formed of serially connected plural stages of scan registers provided on each port at the address input side of said dual port memory corresponding to each node; an address inputting circuit for selectively supplying predetermined pattern data or their inverted pattern data to one port side of said first group of scan registers and the other of said inverted pattern data or said predetermined pattern data to the other port side of said first group of scan registers; a second group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data input side of said dual port memory corresponding to each node; and a data inputting circuit for selectively supplying said predetermined pattern data or said inverted pattern data passed through the one port side of said first group of scan registers to the one port side of said second group of scan registers and selectively supplying, in a first mode, said inverted pattern data or said predetermined pattern data passed through the other port side of said first group of scan registers, and, in a second mode, said predetermined pattern data or said inverted pattern data passed through the other port side of said first group of scan registers, to the other port side of said second group of scan registers, wherein in said first mode, data written from a port A and data written from a port B are always held in inverse relationship to each other; and wherein in said second mode, the same data can be written from port A and port B.
Claim 3
Dependent Claim
42 words
An embedded testing circuit of a dual port memory according to claim 1, wherein said data inputting circuit derives said predetermined pattern data or said inverted pattern data from an intermediate one of the stages of said first group of scan registers.
Claim 4
Dependent Claim
90 words
An embedded testing circuit of a dual port memory according to claim 1, further comprising: a third group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data output side of said dual port memory corresponding to each node, the portions thereof on both ports being serially connected; and a data selector selecting said predetermined pattern data passed through either port side of said first group of scan registers and supplying the selected data to said third group of scan registers.
Claim 5
Dependent Claim
22 words
An embedded testing circuit of a dual port memory according to claim 1, wherein an M-sequence pattern is used as said pattern.
Claim 6
Dependent Claim
300 words
An embedded testing circuit of a dual port memory embedded in a semiconductor integrated circuit together with a dual port memory for testing the memory comprising: a first group of scan registers formed of serially connected plural stages of scan registers provided on each port at the address input side of said dual port memory corresponding to each node; an address inputting circuit for selectively supplying predetermined pattern data or their inverted pattern data to one port side of said first group of scan registers and the other of said inverted pattern data or said predetermined pattern data to the other port side of said first group of scan registers; a second group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data input side of said dual port memory corresponding to each node; and a data inputting circuit for selectively supplying said predetermined pattern data or said inverted pattern data passed through the one port side of said first group of scan registers to the one port side of said second group of scan registers and selectively supplying, in a random data mode, said inverted pattern data or said predetermined pattern data passed through the other port side of said first group of scan registers, and, in a checkerboard mode, said predetermined pattern data or said inverted pattern data passed through the other port side of said first group of scan registers, to the other port side of said second group of scan registers, wherein in said random data mode, data written from a port A and data written from a port B are always held in inverse relationship to each other; and wherein in said checkerboard mode, the same data can be written from port A and port B.
Claim 7
Dependent Claim
300 words
An embedded testing circuit of a dual port memory embedded in a semiconductor integrated circuit together with a dual port memory for testing the memory comprising: a first group of scan registers formed of serially connected plural stages of scan registers provided on each port at the address input side of said dual port memory corresponding to each node; an address inputting circuit for selectively supplying predetermined pattern data or their inverted pattern data to one port side of said first group of scan registers and the other of said inverted pattern data or said predetermined pattern data to the other port side of said first group of scan registers; a second group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data input side of said dual port memory corresponding to each node; and a data inputting circuit for selectively supplying said predetermined pattern data or said inverted pattern data passed through the one port side of said first group of scan registers to the one port side of said second group of scan registers and selectively supplying, in a random data mode, said inverted pattern data or said predetermined pattern data passed through the other port side of said first group of scan registers, and, in a checkerboard mode, said predetermined pattern data or said inverted pattern data passed through the other port side of said first group of scan registers, to the other port side of said second group of scan registers, wherein in said random data mode, data written from a port A and data written from a port B are always held in inverse relationship to each other; and wherein in said checkerboard mode, the same data can be written from port A and port B.
Claim 8
Dependent Claim
42 words
An embedded testing circuit of a dual port memory according to claim 5, wherein said data inputting circuit derives said predetermined pattern data or said inverted pattern data from an intermediate one of the stages of said first group of scan registers.
Claim 9
Dependent Claim
90 words
An embedded testing circuit of a dual port memory according to claim 5, further comprising: a third group of scan registers formed of serially connected plural stages of scan registers provided on each port at the data output side of said dual port memory corresponding to each node, the portions thereof on both ports being serially connected; and a data selector selecting said predetermined pattern data passed through either port side of said first group of scan registers and supplying the selected data to said third group of scan registers.
Claim 10
Dependent Claim
22 words
An embedded testing circuit of a dual port memory according to claim 5, wherein an M-sequence pattern is used as said pattern.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |