US5587948A
Expired / Lapsed
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Nonvolatile semiconductor memory with NAND structure memory arrays
Assignee: Toshiba Corp
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Filing: 1995-06-14
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Granted: 1996-12-24
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Expires: 2015-06-14
Abstract
Abstract A memory cell section is divided into a data storage area and a data management information storage area in a column direction. The number of memory cells of each of NAND strings of the data management information storage area is smaller than that of memory cells of each of NAND strings of the data storage area. Word lines are connected in common to NAND strings arranged in the column direction in the data storage area, and two of them extend to be connected in common to the NAND strings arranged in the column direction in the data management information storage area. Bit lines are connected in common to the NAND strings arranged in the row direction.
Inventors
- 👤 Hiroto Nakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
157 words
A nonvolatile semiconductor memory comprising: a first bit line; a second bit line; a plurality of select gate lines; a source line; a memory cell array comprising a plurality of first NAND strings in a first memory cell area and a plurality of second NAND strings in a second memory cell area, each of the first NAND strings comprising a select gate transistor and i nonvolatile memory cells, which are connected in series between said first bit line and said source line, each of the second NAND strings comprising a select gate transistor and j nonvolatile memory cells, which are connected in series between said second bit line and said source line, said i nonvolatile memory cells being greater in number than said j nonvolatile memory cells; and decoding means for selecting those of said first NAND strings and those of said second NAND strings, which are connected to a selected one of said select gate lines.
Claim 2
Dependent Claim
157 words
A nonvolatile semiconductor memory comprising: a first bit line; a second bit line; a plurality of select gate lines; a source line; a memory cell array comprising a plurality of first NAND strings in a first memory cell area and a plurality of second NAND strings in a second memory cell area, each of the first NAND strings comprising a select gate transistor and i nonvolatile memory cells, which are connected in series between said first bit line and said source line, each of the second NAND strings comprising a select gate transistor and j nonvolatile memory cells, which are connected in series between said second bit line and said source line, said i nonvolatile memory cells being greater in number than said j nonvolatile memory cells; and decoding means for selecting those of said first NAND strings and those of said second NAND strings, which are connected to a selected one of said select gate lines.
Claim 3
Dependent Claim
47 words
The nonvolatile semiconductor memory according to claim 1, wherein said first NAND strings constitute a first memory cell array and said second NAND strings constitute a second memory cell array, and the first memory cell array and the second memory cell array are contiguous to each other.
Claim 4
Dependent Claim
66 words
The nonvolatile semiconductor memory according to claim 1, further comprising a plurality of first word lines each connected to those of said nonvolatile memory cells of said first and second NAND strings, which are arranged in a row, and a plurality of second word lines each connected only to those of said nonvolatile memory cells of said first NAND strings, which are arranged in a row.
Claim 5
Dependent Claim
66 words
The nonvolatile semiconductor memory according to claim 2, further comprising a plurality of first word lines each connected to those of said nonvolatile memory cells of said first and second NAND strings, which are arranged in a row, and a plurality of second word lines each connected only to those of said nonvolatile memory cells of said first NAND strings, which are arranged in a row.
Claim 6
Dependent Claim
60 words
The nonvolatile semiconductor memory according to claim 4, wherein said first memory cell array is interposed between said decoding means and said second memory cell array, and said first word lines extend from said decoding means to said second memory cell array and said second word lines extend from said decoding means and terminate at the first memory cell array.
Claim 7
Dependent Claim
41 words
The nonvolatile semiconductor memory according to claim 5, further comprising means for performing read, write and erase operations simultaneously with respect to said nonvolatile memory cell of one of said first and second memory cell arrays selected by said decoding means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |