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US5589700A
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Semiconductor nonvolatile memory
Assignee: Rohm Co Ltd
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Filing: 1994-02-28
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Granted: 1996-12-31
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Expires: 2014-02-28
Abstract
Abstract A semiconductor nonvolatile memory comprised of a p-type silicon substrate 3, an n + drain 5 and an n + source 9, the source and the drain regions defining an MOS channel region 7. On top of the channel region 7 there are laminated a silicon dioxide film 18 and a semiconductor rich oxide film 20 which has been nitrided so as to leave silicon nitride region therein. Further on top of these layers, there is formed a polysilicon film 22, which is etched to form a control electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory (EPROM) is constructed.
Inventors
- 👤 Hironobu Nakao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
77 words
A semiconductor device including a nonvolatile memory, comprising: a first conductivity type semiconductor region; a pair of second conductivity type diffusion regions formed within said first conductivity type semiconductor region; an insulating layer formed on said first conductivity type semiconductor region; a charge trapping layer comprising a plurality of silicon nitride regions formed within a silicon dioxide layer, said charge trapping layer formed on said insulating layer, and a control electrode formed on said charge trapping layer.
Claim 2
Dependent Claim
77 words
A semiconductor device including a nonvolatile memory, comprising: a first conductivity type semiconductor region; a pair of second conductivity type diffusion regions formed within said first conductivity type semiconductor region; an insulating layer formed on said first conductivity type semiconductor region; a charge trapping layer comprising a plurality of silicon nitride regions formed within a silicon dioxide layer, said charge trapping layer formed on said insulating layer, and a control electrode formed on said charge trapping layer.
Claim 3
Dependent Claim
80 words
A semiconductor device including a nonvolatile memory according to claim 1, wherein said pair of second conductivity type diffusion regions are source and drain regions, so that an MOS channel may be formed between the source and the drain regions under predetermined voltage conditions, and wherein charges may be trapped in said charge trapping layer under predetermined voltage conditions thereby altering the threshold voltage of said MOS channel such that data may be stored in nonvolatile manner in said memory.
Claim 4
Dependent Claim
85 words
A semiconductor device including a nonvolatile memory, comprising: a first conductivity type semiconductor substrate region; a pair of second conductivity type diffusion regions formed within said first conductivity type semiconductor substrate region; a gate oxide insulating layer formed on said first conductivity type semiconductor substrate region; a charge trapping layer comprising silicon nitride regions formed within a silicon dioxide layer, said charge trapping layer formed on said gate oxide insulating layer and in electrical contact therewith; a control electrode formed on said charge trapping layer.
Claim 5
Dependent Claim
85 words
A semiconductor device including a nonvolatile memory, comprising: a first conductivity type semiconductor substrate region; a pair of second conductivity type diffusion regions formed within said first conductivity type semiconductor substrate region; a gate oxide insulating layer formed on said first conductivity type semiconductor substrate region; a charge trapping layer comprising silicon nitride regions formed within a silicon dioxide layer, said charge trapping layer formed on said gate oxide insulating layer and in electrical contact therewith; a control electrode formed on said charge trapping layer.
References Cited (Backward Citations)
WO1982004162A1
Cited
US5319230A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |