US5589850A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for converting two dimensional pixel image into one-dimensional pixel array
Assignee: Industrial Technology Research Institute
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Filing: 1994-09-26
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Granted: 1996-12-31
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Expires: 2014-09-26
Abstract
Abstract An converter apparatus to convert the (X, Y) coordinate of the two-dimensional screen position of a pixel to a linear address. The converter apparatus, which can be used with a variety of video displays of various resolutions including 1280x1024, 1152x900, 640x480, 1024x768, 1600x1280, and 800x600, contains three circuits in parallel disposition to receive and process various portions of the X and Y bits, and to output a Z-bit linear address. The first circuit mainly contains a multiplexer and it receives lower X bits as inputs; the second circuit contains a plurality of adders and multiplexers and a logical operation circuit, and it receives higher X bits and lower Y bits as inputs; and the third circuit mainly contains a multiplexer and it receives higher Y bits and at least a portion of the lower Y bits as inputs. The converter apparatus does not require a system CPU thus very high speed conversion can be achieved.
Inventors
- 👤 Lie-Der Lin
- 👤 Jiunn-Ming Ju
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:15
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0207; G09; G09G; G09G5/00; G09G5/36; G09G5/39
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
387 words
A converter apparatus for use with a computer display screen to convert coordinates of two-dimensional pixels of a graphic image to linear address, each of said pixels being represented by a first coordinate and a second coordinate, said first coordinate having an X-bit address and said second coordinate having a Y-bit address, said X bits consisting of lower X bits and higher X bits, and said Y bits consisting of lower Y bits and higher Y bits, each of said linear addresses having Z bits consisting of lower Z bits, middle Z bits, and higher Z bits, said converter apparatus comprising: (a) a first circuit to receive said lower X bits of various resolutions as inputs, and to output said lower Z bits; (b) a second circuit to receive said higher X bits and said lower Y bits as inputs, also of various resolutions, and to output said middle Z bits and a first carrier bit; (c) a third circuit to receive said upper Y bits and a portion of said lower Y bits, also of various resolutions, and null bits as inputs, and to output precursory higher Z bits; (d) a first adder circuit to receive said precursory Z bits, said Y bits and said first carrier bit as inputs, and to output said higher Z bits; and (e) a second adder circuit to receive said lower Z bits, said middle Z bits and said higher Z bits as inputs, and to output said Z-bit linear address; (f) wherein said first circuit, said second circuit, and said third circuit all being connected to a resolution select to select one of said inputs respectively connected thereto; (g) said second circuit comprises a second multiplexer, a third. multiplexer, a fourth multiplexer, a third adder circuit, and a logical operation circuit; (h) said third adder circuit being adapted to receive outputs from said second, third, and fourth multiplexers as inputs, and to output said middle Z bits minus the highest middle Z bit, a special Z bit corresponding said highest middle Z bit, and a second carrier bit; and (i) said logical operation circuit being adapted to receive said special Z bit, said second carrier bit, and a portion of said higher X bits as inputs, and to output said first carrier bit and said highest middles Z bits.
Claim 2
Dependent Claim
387 words
A converter apparatus for use with a computer display screen to convert coordinates of two-dimensional pixels of a graphic image to linear address, each of said pixels being represented by a first coordinate and a second coordinate, said first coordinate having an X-bit address and said second coordinate having a Y-bit address, said X bits consisting of lower X bits and higher X bits, and said Y bits consisting of lower Y bits and higher Y bits, each of said linear addresses having Z bits consisting of lower Z bits, middle Z bits, and higher Z bits, said converter apparatus comprising: (a) a first circuit to receive said lower X bits of various resolutions as inputs, and to output said lower Z bits; (b) a second circuit to receive said higher X bits and said lower Y bits as inputs, also of various resolutions, and to output said middle Z bits and a first carrier bit; (c) a third circuit to receive said upper Y bits and a portion of said lower Y bits, also of various resolutions, and null bits as inputs, and to output precursory higher Z bits; (d) a first adder circuit to receive said precursory Z bits, said Y bits and said first carrier bit as inputs, and to output said higher Z bits; and (e) a second adder circuit to receive said lower Z bits, said middle Z bits and said higher Z bits as inputs, and to output said Z-bit linear address; (f) wherein said first circuit, said second circuit, and said third circuit all being connected to a resolution select to select one of said inputs respectively connected thereto; (g) said second circuit comprises a second multiplexer, a third. multiplexer, a fourth multiplexer, a third adder circuit, and a logical operation circuit; (h) said third adder circuit being adapted to receive outputs from said second, third, and fourth multiplexers as inputs, and to output said middle Z bits minus the highest middle Z bit, a special Z bit corresponding said highest middle Z bit, and a second carrier bit; and (i) said logical operation circuit being adapted to receive said special Z bit, said second carrier bit, and a portion of said higher X bits as inputs, and to output said first carrier bit and said highest middles Z bits.
Claim 3
Dependent Claim
14 words
The converter apparatus of claim 1 wherein said first circuit comprises a first multiplexer.
Claim 4
Dependent Claim
24 words
The converter apparatus of claim 1 wherein said third adder circuit comprises an AND gate, an OR gate, and a plurality of full adders.
Claim 5
Dependent Claim
13 words
The converter apparatus of claim 3 which further comprises an exclusive OR gate.
Claim 6
Dependent Claim
21 words
The converter apparatus of claim 3 wherein said logical circuit comprises a plurality of half adders and a plurality of multiplexers.
Claim 7
Dependent Claim
14 words
The converter apparatus of claim 1 wherein said third circuit comprises a fifth multiplexer.
Claim 8
Dependent Claim
24 words
The converter apparatus of claim 1 which is adapted to work with video displays having resolutions of 1280×1024, 1152×900, 640×480, 1024×768, 1600×1280, or 800×600.
Claim 9
Dependent Claim
22 words
The converter apparatus of claim 1 which is adapted to work with video displays having resolutions of 1280×1024, 1152×900, 640×480, or 1024×768.
Claim 10
Dependent Claim
349 words
A converter apparatus for use with a computer display screen to convert coordinates of two-dimensional pixels of a graphic image to linear address, each of said pixels being represented by a first coordinate and a second coordinate, said first coordinate having an X-bit address and said second coordinate having a Y-bit address, said X bits consisting of lower X bits and higher X bits, and said Y bits consisting of lower Y bits and higher Y bits, each of said linear addresses having Z bits consisting of lower Z bits, middle Z bits, and higher Z bits, said convertor apparatus comprising: (a) a first circuit to receive said lower X bits of various resolutions as inputs, and to output said lower Z bits; (b) a second circuit to receive said higher X bits and said lower Y bits as inputs, also of various resolutions, and to output said middle Z bits and a first carrier bit; (c) a third circuit to receive said upper Y bits and a portion of said lower Y bits, also of various resolutions, and null bits as inputs, and to output precursory higher Z bits; (d) a first adder circuit to receive said precursory Z bits, said Y bits and said first carrier bit as inputs, and to output said higher Z bits; and (e) a second adder circuit to receive said lower Z bits, said middle Z bit and said higher Z bits as inputs, and to output said Z-bit linear address; (f) wherein said first circuit, said second circuit, and said third circuit all being connected to a resolution select to select one of said inputs respectively connected thereto; (g) said converter further comprises a fourth adder circuit, said fourth adder circuit being adapted to receive said lower Y bits, said second carrier bit, and said Y bits minus the lowest Y bit as inputs, and to output special (Y-1) bits to said third circuit, said special (Y-1) bits corresponding to said Y bits minus the lowest Y bit; and said third circuit is further adapted to receive said special (Y-1) bits.
Claim 11
Dependent Claim
349 words
A converter apparatus for use with a computer display screen to convert coordinates of two-dimensional pixels of a graphic image to linear address, each of said pixels being represented by a first coordinate and a second coordinate, said first coordinate having an X-bit address and said second coordinate having a Y-bit address, said X bits consisting of lower X bits and higher X bits, and said Y bits consisting of lower Y bits and higher Y bits, each of said linear addresses having Z bits consisting of lower Z bits, middle Z bits, and higher Z bits, said convertor apparatus comprising: (a) a first circuit to receive said lower X bits of various resolutions as inputs, and to output said lower Z bits; (b) a second circuit to receive said higher X bits and said lower Y bits as inputs, also of various resolutions, and to output said middle Z bits and a first carrier bit; (c) a third circuit to receive said upper Y bits and a portion of said lower Y bits, also of various resolutions, and null bits as inputs, and to output precursory higher Z bits; (d) a first adder circuit to receive said precursory Z bits, said Y bits and said first carrier bit as inputs, and to output said higher Z bits; and (e) a second adder circuit to receive said lower Z bits, said middle Z bit and said higher Z bits as inputs, and to output said Z-bit linear address; (f) wherein said first circuit, said second circuit, and said third circuit all being connected to a resolution select to select one of said inputs respectively connected thereto; (g) said converter further comprises a fourth adder circuit, said fourth adder circuit being adapted to receive said lower Y bits, said second carrier bit, and said Y bits minus the lowest Y bit as inputs, and to output special (Y-1) bits to said third circuit, said special (Y-1) bits corresponding to said Y bits minus the lowest Y bit; and said third circuit is further adapted to receive said special (Y-1) bits.
Claim 12
Dependent Claim
24 words
The converter apparatus of claim 9 which is adapted to work with video displays having resolutions of 1280×1024, 1152×900, 640×480, 1024×768, 1600×1280, or 800×600.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |