Method and system for user programmable design verification for printed circuit boards and multichip modules

Claim 2

In an computer aided design system for the design of an electronic circuit, a method of verifying design constraints in the electronic circuit, the electronic circuit including a selected plurality of interconnected components, the method comprising the steps of: defining a design constraint for a component of the electronic circuit; providing a verification engine for executing a verification procedure verifying the design constraint of the component; providing a programming interface for defining the verification procedure verifying the design constraint; defining the verification procedure in the programming interface, the verification procedure remaining independent of the verification engine until execution of the verification procedure; and executing the verification procedure with the verification engine to verify the design constraint.

Claim 3

The method of claim 1 wherein the step of defining a design constraint further comprises the steps of: selecting a component type in the electronic circuit; defining a design constraint for components of the selected component type; and designating a verification procedure for verifying the design constraint for the selected component type.

Claim 4

The method of claim 1, wherein the step of defining the verification procedure comprises the steps of: designating a design constraint for verification; defining a verification procedure for verifying that a component satisfies the designated design constraint applicable to the component; and, registering the verification procedure into a constraint verification library.

Claim 5

The method of claim 1, further comprising the steps of: defining for a design constraint of a component in the circuit a precedence value for ordering the verification of the design constraint with respect to other design constraints such that the design constraint of a component having a highest precedence is used to verify the component.

Claim 6

The method of claim 1, wherein the step of executing a verification procedure with the verification engine further comprises the steps of: determining the design constraint applicable to the component; retrieving the verification procedure applicable to design constraint from a constraint verification library; determining an actual value of the component with respect to the design constraint, using the verification procedure; and determining if the actual value of the component violates the design constraint.

Claim 7

A computer automated design system for verifying design constraints in an electronic circuit, the electronic circuit including a selected plurality of interconnected components, the system comprising: a processor for executing stored verification procedures, and for retrieving data from memory; a component library memory, operatively coupled to the processor, for storing a database of components for creating an electronic circuit, each component having a component type, and a design constraint; a circuit memory, operatively coupled to the processor and the component library memory, for storing an electronic circuit as a hierarchy of interconnected components, each first component inheriting the design constraints of any second component including the first component; a constraint memory, operatively coupled to the processor, for storing a design constraint for a component of the electronic circuit; a programming interface, managed by the processor, for defining the verification procedure verifying the design constraint; a procedure memory, operatively coupled to the programming interface, for storing the defined verification procedure; and a verification engine, operatively coupled to the processor and the procedure memory, for controlling the processor to retrieve from the procedure memory and execute a verification procedure verifying the design constraint of the component.

Claim 8

A computer automated design system for verifying design constraints in an electronic circuit, the electronic circuit including a selected plurality of interconnected components, the system comprising: a processor for executing stored verification procedures, and for retrieving data from memory; a component library memory, operatively coupled to the processor, for storing a database of components for creating an electronic circuit, each component having a component type, and a design constraint; a circuit memory, operatively coupled to the processor and the component library memory, for storing an electronic circuit as a hierarchy of interconnected components, each first component inheriting the design constraints of any second component including the first component; a constraint memory, operatively coupled to the processor, for storing a design constraint for a component of the electronic circuit; a programming interface, managed by the processor, for defining the verification procedure verifying the design constraint; a procedure memory, operatively coupled to the programming interface, for storing the defined verification procedure; and a verification engine, operatively coupled to the processor and the procedure memory, for controlling the processor to retrieve from the procedure memory and execute a verification procedure verifying the design constraint of the component.

Claim 9

The system of claim 6, further comprising: constraint definition means, operatively coupled to the constraint memory and the processor, for defining a design constraint for components of the selected component type.

Claim 10

The system of claim 6, wherein programming interface further comprises: verification registration means, operatively coupled to the procedure memory and the design verification engine, for linking a verification procedure in stored in the procedure memory with at least one constraint stored in the constraint memory, wherein the verification procedure is retrieved from the procedure memory when a constraint in the constraint memory is passed to the verification engine for verification.

Claim 11

The system of claim 6, further comprising: precedence means, operatively coupled to the constraint memory and the processor, for defining for a design constraint of a component in the circuit a precedence value for ordering the verification of the design constraint with respect to other design constraints, such that the design constraint of a component having a highest precedence is used to verify the component, the precedence value stored in association with the design constraint in the constraint memory.