US5590067A
Expired / Lapsed
US
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Method and arrangement for transformation of signals from a frequency to a time domain
Assignee: Chartoleaux KG LLC
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Filing: 1995-03-14
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Granted: 1996-12-31
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Expires: 2015-03-14
Abstract
Abstract An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by √ 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of √ 2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
Inventors
- 👤 Anthony M. Jones
- 👤 Kevin D. Dewar
- 👤 Martin W. Sotheran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:53
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/147
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
167 words
A system for use in transforming digital signals from a frequency to a time representation, in which the digital signals are arranged in groups of N data input words, comprising: common processing means (CBLK) having a plurality of common arithmetic devices (BT2, BT3, cIs, c3s) arranged to pass both odd- and even-numbered input data words in separate passes to form odd and even common processing means output values, respectively; pre-common processing means (PREC) arranged to perform predetermined pairing operations on odd-numbered ones of the input words and to transmit even-numbered ones of the input words to pre-common outputs; and post-common processing means (POSTC) arranged to perform predetermined output scaling operations on the odd common processing means output values to form post-processed odd values and to arithmetically combine the post-processed odd values with the even common processing means output values to generate high- and low-order output words, the system being arranged such that the output words contain inverse discrete cosine transformation values corresponding to the input data words.
Claim 2
Independent Claim
167 words
A system for use in transforming digital signals from a frequency to a time representation, in which the digital signals are arranged in groups of N data input words, comprising: common processing means (CBLK) having a plurality of common arithmetic devices (BT2, BT3, cIs, c3s) arranged to pass both odd- and even-numbered input data words in separate passes to form odd and even common processing means output values, respectively; pre-common processing means (PREC) arranged to perform predetermined pairing operations on odd-numbered ones of the input words and to transmit even-numbered ones of the input words to pre-common outputs; and post-common processing means (POSTC) arranged to perform predetermined output scaling operations on the odd common processing means output values to form post-processed odd values and to arithmetically combine the post-processed odd values with the even common processing means output values to generate high- and low-order output words, the system being arranged such that the output words contain inverse discrete cosine transformation values corresponding to the input data words.
Claim 3
Dependent Claim
42 words
A system according to claim 1 wherein the pre-common processing means (PREC) has means arranged to perform predetermined scaling operations on the odd-numbered ones of the input words and to transmit even-numbered ones of the input words directly to the pre-common outputs.
Claim 4
Dependent Claim
30 words
A system according to claim 2, wherein the post-common processing means (POSTC) has means arranged to perform predetermined output scaling operations only on the odd common processing means output values.
Claim 5
Dependent Claim
41 words
A system according to claim 1, 2 or 3, and comprising a controller (CNTL) that is connected to the pre-common processing means and has means for sorting each group of N input data words into the odd and even-numbered input words.
Claim 6
Dependent Claim
38 words
A system according to claim 4, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input data words.
Claim 7
Independent Claim
73 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) has N/2 pre-common inputs and N/2 pre-common outputs, the common processing means (CBLK) has N/2 common inputs, which are connected to the N/2 pre-common outputs, and the N/2 common outputs and the post-common processing means (POSTC) has N/2 post-common inputs, which are connected to the N/2 common outputs, and N/2 post-common outputs, which form system outputs.
Claim 8
Dependent Claim
41 words
A system according to claim 6, and comprising means arranged to force predetermined bits of selected internal data words to predetermined binary values, such that the statistical accuracy of the system is improved relative to a predetermined test input data set.
Claim 9
Independent Claim
46 words
A system according to any one of claims 1 to 3, and comprising means arranged to force predetermined bits of selected internal data words to predetermined binary values, such that the statistical accuracy of the system is improved relative to a predetermined test input data set.
Claim 10
Dependent Claim
24 words
A system according to claim 8 and arranged such that the selected internal data words are the post-processed odd values and even common outputs.
Claim 11
Dependent Claim
39 words
A system according to claim 8, wherein the pre-common means (PREC) includes a single scaling multiplier (R2MUL) attached in a lowest order input data line for multiplying the lowest order odd input data word by a pre-determined scaling factor.
Claim 12
Independent Claim
44 words
A system according to any one of claims 1 to 3, wherein the pre-common means (PREC) includes a signal scaling multiplier (R2MUL) attached in a lowest order input data line for multiplying the lowest order odd input data word by a pre-determined scaling factor.
Claim 13
Dependent Claim
17 words
A system according to claim 11, wherein the predetermined scaling factor is the square root of two.
Claim 14
Dependent Claim
38 words
A system according to claim 11, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input date words.
Claim 15
Independent Claim
43 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input data words.
Claim 16
Dependent Claim
15 words
A system according to claim 14, the adders (PIA, P2A, P3A) all being fixed-point devices.
Claim 17
Independent Claim
46 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means further includes a plurality of pre-common output storage elements (C1OL, C54L, C32L, C76L) arranged alternately to load and latch the paired input data words and the even input data words.
Claim 18
Independent Claim
36 words
A system according to any one claims 1 to 3, wherein the common processing means (CBLK) includes common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) for multiplying selected common processing means inputs values by predetermined trigonometric constants.
Claim 19
Dependent Claim
47 words
A system according to claim 17, wherein the common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) are four in number and are arranged such that each of a selected pair of the common processing means input values is connected to a corresponding pair of the four coefficient multipliers.
Claim 20
Dependent Claim
107 words
A system according to claim 18, wherein: a) the post-common processing means (POSTC) includes switchable arithmetic devices (S70A, S61A, S43A, S52A) each with an addition mode and a subtraction mode; b) the post-processed odd values and the even common outputs are connected as inputs to the switchable arithmetic devices (S70A, S61A, S43A, S52A); c) in the addition mode, the switchable arithmetic devices from the low-order output words as the sum of the post-processed odd values and--the even common outputs; and d) in the subtraction mode, the switchable arithmetic devices form the high-order output words as the difference of the post-processed odd values and the even common outputs.
Claim 21
Dependent Claim
18 words
A system according to claim 17, the common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) all being fixed-point devices.
Claim 22
Dependent Claim
107 words
A system according to claim 17, wherein: a) the post-common processing means (POSTC) includes switchable arithmetic devices (S70A, S61A, S43A, S52A) each with an addition mode and a subtraction mode; b) the post-processed odd values and the even common outputs are connected as inputs to the switchable arithmetic devices (S70A, S61A, S43A, S52A); c) in the addition mode, the switchable arithmetic devices form the low-order output words as the sum of the post-processed odd values and--the even common outputs; and d) in the subtraction mode, the switchable arithmetic devices form the high-order output words as the difference of the post-processed odd values and the even common outputs.
Claim 23
Dependent Claim
46 words
A system according to claim 17, wherein the post-common processing means (POSTC) includes a plurality of post-common coefficient multipliers (dI, d3, d5, d7) arranged to multiply the odd common processing means output values respectively by predetermined post-common, constant, scaling values to form the post-processed odd values.
Claim 24
Independent Claim
112 words
A system according to any one of claims 1 to 3, wherein: a) the post-common processing means (POSTC) includes switchable arithmetic devices (S70A, S61A, S43A, S52A) each with an addition mode and a subtraction mode; b) the post-processed odd values and the even common outputs are connected as inputs to the switchable arithmetic devices (S70A, S61A, S43A, S52A); c) in the addition mode, the switchable arithmetic devices form the low-order output words as the sum of the post-processed odd values and--the even common outputs; and d) in the subtraction mode, the switchable arithmetic devices form the high-order output words as the difference of the post-processed odd values and the even common outputs.
Claim 25
Dependent Claim
72 words
A system according to claim 23, wherein: a) the post-common processing means (POSTC) includes a first set of output data latches (Lg0, Lg1, Lg2, Lg3) arranged to store the even common outputs and a second set of output data latches (Lh0, Lh1, Lh2, Lh3) arranged to store the post-processed odd values; and b) each of the first and second output data latches is connected to respective inputs of the switchable arithmetic devices.
Claim 26
Dependent Claim
36 words
A system according to claim 23, and comprising control means (CNTL) connected to the switchable arithmetic devices (S70A, S61A, S43A, S52A) for generating mode signals to switch the arithmetic devices between the addition and subtraction modes.
Claim 27
Dependent Claim
18 words
A system according to claim 23, the switchable arithmetic devices (S70A, S61A, S43A, S52A) all being fixed-point devices.
Claim 28
Dependent Claim
46 words
A system according to claim 23, wherein the post-common processing means (POSTC) includes a plurality of post-common coefficient multipliers (dI, d3, d5, d7) arranged to multiply the odd common processing means output values respectively by predetermined post-common, constant, scaling values to form the post-processed odd values.
Claim 29
Dependent Claim
19 words
A system according to claim 23, wherein the switchable arithmetic devices (S70A, S61A, S43A, S52A) are all fixed-point devices.
Claim 30
Dependent Claim
19 words
A system according to claim 23, wherein the common arithmetic devices (BT2, BT3, cIs, c3s) are all fixed-point devices.
Claim 31
Dependent Claim
42 words
A system according to claim 23, further comprising a plurality of adders (M5A, P1A, P2A, P3A, BT2, BT3, CSO, CS1, CS2, CS3, RESO, RES1, RES2, RES3, HOA, H1A, H2A, H3A) and adder/subtractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
Claim 32
Independent Claim
51 words
A system according to any one of claims 1 to 3, wherein the post-common processing means (POSTC) includes a plurality of post-common coefficient multipliers (dI, d3, d5, d7) arranged to multiply the odd common processing means output values respectively by predetermined post-common, constant, scaling values to form the post-processed odd values.
Claim 33
Independent Claim
20 words
A system according to any one of claims 1-3, wherein the common processing means (CBLK) is a non-clocked, pure-logic circuit.
Claim 34
Independent Claim
20 words
A system according to any one claims 1-3, the common arithmetic devices (BT2, BT3, cIs, c3s) all being fixed-point devices.
Claim 35
Independent Claim
45 words
A system according to any one of claims 1-3, and comprising a plurality of adders (M5A, PIA, P2A, P3A, BT2, BT3, CSO, CS1, CS2, CS3, RESO, RES1, RES2, RES3, HOA, H1A, H2A, H3A) and adder/subtractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
Claim 36
Independent Claim
32 words
A system according to any of claims 1-3, and including a transmission device arranged to transmit the digital signals, and a receiver which is connected to a system output of the system.
Claim 37
Independent Claim
78 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input data words, and the common processing means (CBLK) includes common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) for multiplying selected common processing means input values by predetermined trigonometric constants, the adders (P1A, P2A, P3A) all being fixed-point devices.
Claim 38
Independent Claim
153 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input data words, the adders (PIA, P2A, P3A) all being fixed-point devices, and a) the post-common processing means (POSTC) includes switchable arithmetic devices (S70A, S61A, S43A, S52A) each with an addition mode and a subtraction mode; b) the post-processed odd values and the even common outputs are connected as inputs to the switchable arithmetic devices (S70A, S61A, S43A, S52A); c) in the addition mode, the switchable arithmetic devices form the low-order output words as the sum of the post-processed odd values and--the even common outputs; and d) in the subtraction mode, the switchable arithmetic devices form the high-order output words as the difference of the post-processed odd values and the even common outputs.
Claim 39
Independent Claim
63 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input data words, the adders (PIA, P2A, P3A) all being fixed-point devices; and the common processing means (CBLK) is a non-clocked, pure-logic circuit.
Claim 40
Independent Claim
150 words
A system according to any one of claims 1 to 3, wherein the common processing means (CBLK) includes common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) for multiplying selected common processing means input values by predetermined trigonometric constants, the common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) all being fixed-point devices, wherein: a) the post-common processing means (POSTC) includes switchable arithmetic devices (S70A, S61A, S43A, S52A) each with an addition mode and a subtraction mode; b) the post-processed odd values and the even common outputs are connected as inputs to the switchable arithmetic devices (S70A, S61A, S43A, S52A); c) in the addition mode, the switchable arithmetic devices form the low-order output words as the sum of the post-processed odd values and--the even common outputs; and d) in the subtraction mode, the switchable arithmetic devices form the high-order output words as the difference of the post-processed odd values and the even common outputs.
Claim 41
Independent Claim
89 words
A system according to any one of claims 1 to 3, wherein the pre-common processing means (PREC) includes a plurality of adders (P1A, P2A, P3A) for pairwise addition of predetermined ones of the odd-numbered input data words to form paired input date, the adders (PIA, P2A, P3A) all being fixed-point devices; wherein the common processing means (CBLK) includes common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) for multiplying selected common processing means input values by predetermined trigonometric constants, the common coefficient multipliers (MULC1S, MULC3S3, MULC3S2, MULNC1S) all being fixed-point devices.
Claim 42
Dependent Claim
19 words
A system according to claim 40, wherein the switchable arithmetic devices (S70A, S61A, S43A, S52A) are all fixed-point devices.
Claim 43
Dependent Claim
19 words
A system according to claim 41, wherein the common arithmetic devices (BT2, BT3, cIs, c3s) are all fixed-point devices.
Claim 44
Dependent Claim
42 words
A system according to claim 42, further comprising a plurality of adders (M5A, PIA, P2A, P3A, BT2, BT3, CSO, CS1, CS2, CS3, RESO, RES1, RES2, RES3, HOA, H1A, H2A, H3A) and adder/subtractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
Claim 45
Dependent Claim
19 words
A system according to claim 40, wherein the common arithmetic devices (BT2, BT3, cIs, c3s) are all fixed-point devices.
Claim 46
Dependent Claim
41 words
A system according to claim 44, further comprising a plurality of adders (M5A, PIA, P2A, P3A, BT2, BT3, CSO, CS1, CS3, RESO, RES1, RES2, RES3, H0A, H1A, H2A, H3A) and adder/subtractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
Claim 47
Dependent Claim
42 words
A system according to claim 40, further comprising a plurality of adddress (M5A, PIA, P2A, P3A, BT2, BT3, CSO, CS1, CS2, CS3, RESO, RES1, RES2, RES3, HOA, H1A, H2A, H3A) and adder/substractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
Claim 48
Dependent Claim
21 words
A system according to any of claim 1-3, wherein the common arithmetic devices (BT2, BT3, cIs, c3s) are all fixed-point devices.
Claim 49
Independent Claim
45 words
A system according to any one of claims 1-3, further comprising a plurality of adders (M5A, PIA, P2A, P3A, BT2, BT3, CSO, CS1, CS2, CS3, RESO, RES1, RES2, RES3, HOA, H1A, H2A, H3A) and adder/subtractors (S70A, S61A, S43A, S52A) all of which are fixed-point devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |