Wafer burn-in test circuit of a semiconductor memory device

Claim 2

A burn-in test circuit for sensing a defective cell of a semiconductor memory device having a plurality of memory cells connected to a word line and a row decoder for selecting the word line, said burn-in test circuit comprising: a word line driver circuit having an input coupled to receive a row decoding signal generated by the row decoder, and an output node coupled to the word line, said row decoding signal having a first state during a normal mode of operation and a second state different than said first state during a burn-in test mode of operation, said word line driver circuit including: a word line boosting voltage transferring circuit coupled to receive an enable voltage and to said output node and being controlled by said row decoding signal, said word line boosting voltage transferring circuit being responsive to said row decoding signal in said normal mode of operation to raise said word line to a voltage level of said enable voltage, and a current pass circuit coupled between said output node and a discharge node and being controlled by said row decoding signal, said current pass circuit being responsive to said row decoding signal in said burn-in test mode of operation to connect said word line to said discharge node; a control circuit having a first input coupled to receive a burn-in voltage, and a second input coupled to receive a control signal; and an electrical line connected between said discharge node of said word line driver circuit and said control circuit said control circuit being responsive to said control signal in said burn-in test mode of operation to apply said burn-in voltage to the word line via said electrical line and said current pass circuit of said word line driver circuit.

Claim 3

The burn-in test circuit as set forth in claim 1, wherein: said word line boosting voltage transferring circuit comprises an input transistor having a first electrode coupled to receive said enable voltage, a gate electrode coupled to receive said row decoding signal, and a second electrode; said current pass circuit comprises a current pass transistor having a first electrode coupled to said second electrode of said input transistor, a gate electrode coupled to receive said row decoding signal, and a second electrode coupled to said electrical line; and, wherein said output node of said word line driver circuit is intermediate said input transistor and said current pass transistor.

Claim 4

The burn-in test circuit as set forth in claim 1, wherein: said word line boosting voltage transferring circuit comprises an input transistor having a first electrode coupled to receive said enable voltage, a gate electrode coupled to receive said row decoding signal, and a second electrode; said current pass circuit comprises a pair of current pass transistors each having a first electrode commonly coupled to said second electrode of said input transistor, and a second electrode commonly coupled to said electrical line; wherein a first one of said current pass transistors has a gate electrode coupled to receive said row decoding signal, and a second one of said current pass transistors has a gate electrode coupled to receive a complement enable signal which is the logical inverse of said enable voltage; and, wherein said output node of said word line driver circuit is intermediate said input transistor and said current pass transistors.

Claim 5

The burn-in test circuit as set forth in claim 3, wherein said control circuit includes: a burn-in control transistor having a first electrode coupled to said first input of said control circuit, a gate electrode coupled to said second input of said control circuit, and a second electrode coupled to said electrical line; and, a discharge transistor having a first electrode coupled to said electrical line, a gate electrode coupled to a complement control signal which is the logical inverse of said control signal, and a second electrode coupled to a reference potential.

Claim 6

The burn-in test circuit as set forth in claim 4, wherein: in said normal mode of operation, said input transistor is turned on, said discharge transistor is turned on, said current pass transistors are turned off, and said burn-in control transistor is turned off; and, in said burn-in test mode of operation, said input transistor is turned off, said discharge transistor is turned off, said current pass transistors are turned on, and said burn-in control transistor is turned on.

Claim 7

The burn-in test circuit as set forth in claim 5, wherein said enable voltage comprises a word line boosting voltage.

Claim 8

The burn-in test circuit as set forth in claim 6, wherein said burn-in voltage is ≧ said word line boosting voltage.

Claim 9

The burn-in test circuit as set forth in claim 6, wherein said burn-in voltage is greater than said word line boosting voltage.

Claim 10

The burn-in test circuit as set forth in claim 1, wherein: said enable voltage comprises a word line boosting voltage; and, said burn-in voltage is greater than said word line boosting voltage.

Claim 11

The burn-in test circuit as set forth in claim 1, wherein: said enable voltage comprises a word line boosting voltage; and, said burn-in voltage is ≧ than said word line boosting voltage.

Claim 12

The burn-in test circuit as set forth in claim 5, wherein said current pass transistors, said burn-in control transistor, and said discharge transistor each comprise an NMOS transistor, and said input transistor comprises a PMOS transistor.

Claim 13

A burn-in test circuit for sensing a defective cell of a semiconductor memory device having a plurality of memory cells connected to a word line and a row decoder for selecting the word line, said burn-in test circuit comprising: a word line driver circuit including word line boosting voltage input means and current pass means connected in series between a word line boosting voltage and an electrical line, said word line driver circuit having an output intermediate said word line boosting voltage input means and said current pass means, said output being coupled to the word line; a control circuit including discharge means connected between said electrical line and a reference potential, and burn-in control means connected between said electrical line and a burn-in voltage; wherein, in a normal mode of operation, said word line boosting voltage input means is turned on by said row decoding signal, said current pass means is turned off by said row decoding signal and a complement word line boosting voltage which is the logical inverse of said word line boosting voltage, said burn-in control means is turned off by a burn-in enable signal, and said discharge means is turned on by a complement burn-in enable signal which is the inverse of said burn-in enable signal, whereby said output and said word line are driven to said word line boosting voltage; and, wherein, in a burn-in test mode of operation, said word line boosting voltage input means is turned off by said row decoding signal, said current pass means is turned on by said row decoding signal said complement word line boosting voltage, said burn-in control means is turned on by said burn-in enable signal, and said discharge means is turned off by said complement burn-in enable signal, whereby said output and said word line are driven to said burn-in voltage.

Claim 14

A burn-in test circuit for sensing a defective cell of a semiconductor memory device having a plurality of memory cells connected to a word line and a row decoder for selecting the word line, said burn-in test circuit comprising: a word line driver circuit including word line boosting voltage input means and current pass means connected in series between a word line boosting voltage and an electrical line, said word line driver circuit having an output intermediate said word line boosting voltage input means and said current pass means, said output being coupled to the word line; a control circuit including discharge means connected between said electrical line and a reference potential, and burn-in control means connected between said electrical line and a burn-in voltage; wherein, in a normal mode of operation, said word line boosting voltage input means is turned on by said row decoding signal, said current pass means is turned off by said row decoding signal and a complement word line boosting voltage which is the logical inverse of said word line boosting voltage, said burn-in control means is turned off by a burn-in enable signal, and said discharge means is turned on by a complement burn-in enable signal which is the inverse of said burn-in enable signal, whereby said output and said word line are driven to said word line boosting voltage; and, wherein, in a burn-in test mode of operation, said word line boosting voltage input means is turned off by said row decoding signal, said current pass means is turned on by said row decoding signal said complement word line boosting voltage, said burn-in control means is turned on by said burn-in enable signal, and said discharge means is turned off by said complement burn-in enable signal, whereby said output and said word line are driven to said burn-in voltage.

Claim 15

The burn-in test circuit as set forth in claim 12, wherein said word line boosting voltage input means comprises a word line boosting voltage input transistor having a first electrode coupled to said word line boosting voltage, a gate electrode coupled to said row decoding signal, and a second electrode.

Claim 16

The burn-in test circuit as set forth in claim 13, wherein said current pass means comprises a pair of current pass transistors each having a first electrode commonly coupled to said second electrode of said word line boosting input transistor, and a second electrode commonly coupled to said electrical line, wherein a first one of said current pass transistors has a gate electrode coupled to said row decoding signal, and a second one of said current pass transistors has a gate electrode coupled to said complement word line boosting signal; and, wherein said output of said word line driver circuit is intermediate said word line boosting input transistor and said current pass transistors.

Claim 17

The burn-in test circuit as set forth in claim 14, wherein said burn-in control means includes a burn-in control transistor having a first electrode coupled to said burn-in voltage, a gate electrode coupled to said burn-in enable signal, and a second electrode coupled to said electrical line.

Claim 18

The burn-in test circuit as set forth in claim 15, wherein said discharge means includes a discharge transistor having a first electrode coupled to said electrical line, a gate electrode coupled to said complement burn-in enable signal, and a second electrode coupled to said reference potential.

Claim 19

The burn-in test circuit as set forth in claim 16, wherein said burn-in voltage is ≧ said word line boosting voltage.

Claim 20

The burn-in test circuit as set forth in claim 16, wherein said burn-in voltage is greater than said word line boosting voltage.

Claim 21

The burn-in test circuit as set forth in claim 12, wherein said burn-in voltage is greater than said word line boosting voltage.

Claim 22

The burn-in test circuit as set forth in claim 16, wherein said current pass transistors, said burn-in control transistor, and said discharge transistor each comprise an NMOS transistor, and said word line boosting voltage input transistor comprises a PMOS transistor.